1.0 JOB/EXPERIMENT NO.
: PC-CSEP402-2020/09
2.0 NAME OF JOB/EXPERIMENT: Building a 4 bit ALU system.
3.0 OBJECTIVE: Building a 4 bit ALU system using VHDL programming.
4.0 PRINCIPLE:
The principle of this assignment is to understand the fundamental principle of Arithmetic Logic Units
(ALUs). ALUs are integral components of computer processors that perform arithmetic and logical
operations. The core principle of an ALU lies in its ability to execute these operations based on the input
data. It achieves this by utilizing various components such as adders, multiplexers, and logic gates. These
components work together to process and manipulate binary data, enabling ALUs to perform addition,
subtraction, multiplication, division, as well as logical operations like AND, OR, and XOR.
The principle of an ALU's operation relies on the concept of data path and control. The data path
represents the flow of data within the ALU, where input operands are processed and the result is
generated. Control signals guide the operations performed by the ALU, ensuring the correct execution of
arithmetic and logical operations based on the given instructions.
Design considerations play a crucial role in ALU architecture, with various design choices impacting the
performance and efficiency of the unit. Different ALU designs, such as ripple carry and carry look-ahead
adders, offer trade-offs in terms of speed, power consumption, and area efficiency. Optimal ALU design
involves balancing these trade-offs to meet specific computational requirements.
The principle of ALU optimization involves techniques such as pipelining, parallel processing, and
instruction-level parallelism. These strategies aim to improve ALU efficiency and throughput by exploiting
parallelism and minimizing idle cycles.
In conclusion, the principle of an ALU revolves around its ability to perform arithmetic and logical
operations based on input data. Understanding the fundamental components, design considerations, and
optimization techniques are essential for utilizing ALUs effectively in computing systems.
4 BIT ALU
32 BIT ALU
5.0 VHDL CODE FOR 4 BIT ALU
--NOT gate
library ieee;
use ieee.std_logic_1164.all;
entity NOT_gate is
port(B : in std_logic;
B_out : out std_logic);
end NOT_gate;
architecture bv of NOT_gate is
begin
B_out<= NOT B;
end bv;
--AND gate
library ieee;
use ieee.std_logic_1164.all;
entity AND_gate is
port(A,B : in std_logic;
AB_out : out std_logic);
end AND_gate;
architecture bv of AND_gate is
begin
AB_out<= A AND B;
end bv;
--OR gate
library ieee;
use ieee.std_logic_1164.all;
entity OR_gate is
port(A,B : in std_logic;
AB_out : out std_logic);
end OR_gate;
architecture bv of OR_gate is
begin
AB_out<= A OR B;
end bv;
--Full Adder
--------------------------
library ieee;
use ieee.std_logic_1164.all;
entity XOR2 is
port(P,Q:in std_logic;
R:out std_logic);
end XOR2;
architecture df of XOR2 is
begin
R<=P XOR Q;
end df;
library ieee;
use ieee.std_logic_1164.all;
entity FA is
port(X,Y,Z:in std_logic;
sum, carry:out std_logic);
end FA;
architecture df of FA is
begin
sum<=X XOR Y XOR Z;
carry<=(X AND Y) OR (Y AND Z) OR (X AND Z);
end df;
library ieee;
use ieee.std_logic_1164.all;
entity composit is
port(B0,B1,B2,B3:in std_logic;
A0,A1,A2,A3,CIN,ASC:in std_logic;
S0,S1,S2,S3,C3:out std_logic);
end composit;
architecture struct of composit is
component XOR2 is
port(P,Q: in std_logic;
R: out std_logic);
end component;
component FA is
port(X,Y,Z:in std_logic;
sum, carry:out std_logic);
end component;
signal Y0,Y1,Y2,Y3,C0,C1,C2:std_logic;
begin
E0: XOR2 port map (B0,ASC,Y0);
E1: XOR2 port map (B1,ASC,Y1);
E2: XOR2 port map (B2,ASC,Y2);
E3: XOR2 port map (B3,ASC,Y3);
FA0: FA port map(Y0,A0,CIN,S0,C0);
FA1: FA port map(Y1,A1,C0,S1,C1);
FA2: FA port map(Y2,A2,C1,S2,C2);
FA3: FA port map(Y3,A3,C2,S3,C3);
end struct;
----------------------------------------
--MUX_4to1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_SOURCE is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
I1,I2,I3,I4 : in STD_LOGIC;
Y : out STD_LOGIC);
end MUX_SOURCE;
architecture Behavioral of MUX_SOURCE is
begin
process (S)
begin
if (S <= "00") then
Y <= I1;
elsif (S <= "01") then
Y <= I2;
elsif (S <= "10") then
Y <= I3;
else
Y <= I4;
end if;
end process;
end Behavioral;
--MUX_2to1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_SOURCE2 is
Port ( S1 : in STD_LOGIC;
I1,I2: in STD_LOGIC;
Y1 : out STD_LOGIC);
end MUX_SOURCE2;
architecture Behavioral of MUX_SOURCE2 is
begin
process(S1)
begin
if (S1 ='0') then
Y1 <= I1;
elsif (S1='1') then
Y1 <= I2;
end if;
end process;
end Behavioral;
-- One bit full adder making
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_1bit is
port(Less,A,B,Cin,Binvert,Ainvert: in std_logic;
S1 : in STD_LOGIC_VECTOR (1 downto 0);
R,Cout: out std_logic);
end ALU_1bit;
architecture struct of ALU_1bit is
--Not gate component
component NOT_gate is
port(B : in std_logic;
B_out : out std_logic);
end component;
--AND gate component
component AND_gate is
port(A,B : in std_logic;
AB_out : out std_logic);
end component;
--or gate
component OR_gate is
port(A,B : in std_logic;
AB_out : out std_logic);
end component;
--FA component
component FA is
port(X,Y,Z:in std_logic;
sum, carry:out std_logic);
end component;
--2:1 MUX component
component MUX_SOURCE2 is
Port ( S1 : in STD_LOGIC;
I1,I2 : in STD_LOGIC;
Y1 : out STD_LOGIC);
end component;
--4:1 MUX component
component MUX_SOURCE is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
I1,I2,I3,I4 : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
signal Abar,Bbar,Asel,Bsel,AB_AND,AB_OR,AB_SUM:std_logic;
begin
NOT1: NOT_gate port map (A,Abar);
NOT2: NOT_gate port map (B,Bbar);
MUX1: MUX_SOURCE2 port map (Ainvert,A,Abar,Asel);
MUX2: MUX_SOURCE2 port map (Binvert,B,Bbar,Bsel);
FA1: FA port map (Asel,Bsel,Cin,AB_SUM);
AND1: AND_gate port map (Asel,Bsel,AB_AND);
OR1: OR_gate port map (Asel,Bsel,AB_OR);
MUX3: MUX_SOURCE port map (S1,AB_AND,AB_OR,AB_SUM,Less,R);
end struct;
--4 input Nor
library ieee;
use ieee.std_logic_1164.all;
entity NOR4 is
port(P,Q,R,S:in std_logic;
T:out std_logic);
end NOR4;
architecture df of NOR4 is
begin
T<=(P NOR Q) NOR (R NOR S);
end df;
--ALU 4 bit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_4bit is
Port (
A, B: in std_logic_vector(3 downto 0);
Op: in std_logic_vector(1 downto 0);
Cin,Ainvert,Binvert: in std_logic;
Less: in std_logic;
Sum: out std_logic_vector(3 downto 0);
Cout,Zero,overflow: out std_logic
);
end ALU_4bit;
architecture Behavioral of ALU_4bit is
component ALU_1bit is
Port (
Less, A, B, Cin, Binvert, Ainvert: in std_logic;
S1: in std_logic_vector(1 downto 0);
R, Cout: out std_logic
);
end component;
-- 4 Nor component
component NOR4 is
port(P,Q,R,S:in std_logic;
T:out std_logic);
end component;
-- xor
component XOR2 is
port(P,Q:in std_logic;
R:out std_logic);
end component;
signal C0, C1, C2,Less1: std_logic;
signal S0, S1, S2, S3,C: std_logic;
begin
ALU1: ALU_1bit port map (Less1, A(0), B(0), Cin, Ainvert, Binvert, Op, S0, C0);
ALU2: ALU_1bit port map (Less1, A(1), B(1), C0, Ainvert, Binvert, Op, S1, C1);
ALU3: ALU_1bit port map (Less1, A(2), B(2), C1, Ainvert, Binvert, Op, S2, C2);
ALU4: ALU_1bit port map (Less1, A(3), B(3), C2, Ainvert, Binvert, Op, S3, C);
Less1<=S3;
NOR_4: NOR4 port map (S0,S1,S2,S3,Zero);
XOR_2: XOR2 port map (C2,C,overflow);
Cout<=C;
Sum <= S3 & S2 & S1 & S0;
end Behavioral;
6.0 OUTPUT WAVE:
7.0 Conclusion :
In conclusion, this assignment has provided us with a comprehensive understanding of Arithmetic Logic Units
(ALUs) and their significance in computer processors. We have explored the core principle of ALUs, focusing on
their architecture, operation, and design considerations. By studying the components such as adders, multiplexers,
and logic gates, we have gained insights into the mechanisms behind ALU functionality, enabling us to perform
arithmetic calculations and logical evaluations. Additionally, we have analyzed different ALU designs, considering
factors such as speed, power consumption, and area efficiency. This has equipped us with the knowledge to make
informed design choices to optimize ALU performance based on specific computational requirements. Furthermore,
we have examined optimization techniques like pipelining, parallel processing, and instruction-level parallelism,
which enhance ALU efficiency and throughput. By applying critical thinking and problem-solving skills, we have
developed the ability to analyze, evaluate, and propose innovative solutions for ALU optimization challenges.
Overall, this assignment has provided us with a solid foundation in ALU principles, empowering us to effectively
utilize and optimize ALUs for diverse computing applications.
