ADVANCED MICROPROCESSORS

Module 1

Abdul Rasheed . A , M.E

Lecturer in Electronics
Govt. Polytechnic College
Palakkad
Architecture
of
Intel 8086
Microprocessor Basics

 The CPU of a microcomputer is made up of a

microprocessor.
 It is a semiconductor device . It fetches, decodes and
executes instructions.
 The basic functional units of a microprocessor are ALU, an
array of registers and a control unit.
 A microprocessor is also featured with a system of buses.
 A bus is a group of wires that carry address, data and
control signals.
 Basically , there are three such buses namely:
Address Bus
Data Bus

Control Bus
History of INTEL Microprocessors

 (1971) 4004 – 4 Bit

 (1972) 8008 – 8 Bit
 (1974) 8080 – 8 Bit
8085 – 8 Bit

 (1978) 8086 – 16 Bit

8088 – 16 Bit
 (1982-89)
80286 – 16 Bit
80386 – 16 Bit
80486 – 32 Bit
 (1993-2001)
Pentium 1-4
Intel 8086 Microprocessor
Key Features:
 Released by Intel in 1978

 Produced from 1978 to 1990s

 A 16-bit microprocessor chip.

 Max. CPU clock rate :

5 MHz to 10 MHz Fig1:Intel 8086 Microprocessor

• Operating voltage:
+5 V dc

 Package: 40 pin DIP

7
Intel 8086
 The first 16 bit processor released by Intel (1978).

 Designed using HMOS technology and contains

approximately 30000 transistors.

 Featured with 20 bit address bus capable of addressing a

maximum of 220 (=1048576 = 1MB) memory locations.

 It uses a 20-bit physical address to directly address 1M

byte of memory .

 Each memory location is 8-bit wide.

8086 microprocessor
Add
Address Bus – 20 lines – A19 – A0 Bus

Data Bus – 16 lines – D15 – D0

Data
Microprocessor Bus
8086

 16 bit- microprocessor ? Control

 16-bits data bus? signals

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 20 bits address bus?
 It can address any one of A19……………A0
1,048,576 (=220 ) memory 0……………….0 00000H
locations/addresses.
 Each memory location is one
byte wide. 1……………….1 FFFFFH
 To store a word of 16 bit 2 00000H
memory locations are
required.
 If the first byte of the word is
at even address 8086 can
read the entire word in one
operation. Memory
 If the first byte of the word is Address
at an odd address, the 8086
will read the first byte with Space
one bus operation and the
second byte with another bus
operation.

1,048,576 memory locations=1MBytes FFFFFH

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Architecture of
Intel 8086
Microprocessor
8086 INTERNAL ARCHITECTURE

2 units are:
1. BIU
2. EU

Fig: 8086 Internal block diagram .

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The 8086 CPU is divided into two independent functional
units:

Bus Interface unit (BIU)

Execution Unit (EU)
Execution Unit
 EU (Execution Unit) of the 8086 tells the BIU where to
fetch instructions or data from, decodes instructions, and
executes instructions.
 The EU contains control circuitry that directs and co-
ordinates internal operations.
 A decoder translates the instructions fetched from
memory into a series of actions and the EU executes
them.
 The EU has a 16 bit ALU that can perform all the
arithmetic and logical operations.
Registers in the 8086 Microprocessor

 In the 8086 microprocessor, the registers are categorized

into mainly four types:

 General Purpose Registers

 Segment Registers
 Pointers and Index Registers
 Flag or Status Register
General Purpose Registers
 The EU has 8 general purpose registers, labeled AH,
AL,BH,BL,CH,CL,DH and DL Which can be used for
temporary storage of 8-bit data.

 The AL register is also known as Accumulator.

 Certain pairs of general purpose register can be used

together to store 16-bit data words.
 ie; AH and AL can be combined to form the 16-bit AX
register .

AH and AL : AX
BH and BL : BX
CH and CL : CX
DH and DL : DX
General Purpose 16-Bit Registers
of 8086
AX

BX AH AL
7 0 7 0

CX

DX AX
15 0
Flag Register

 A flag is a flip-flop that indicates some condition

produced by the execution of an instruction.

 The 8086 has a 16 bit flag register and in this 9 bits are
defined as flags.

 6 flags(Status flags) are used to indicate the status of the

result of arithmetic or logic operations.

 3 flags (Control flags) are used to control certain

operations of the processor.
•Individual bit positions within the flag register
show status of CPU or results of arithmetic
operations.

 Status Flags (Carry, Overflow, Sign, Zero,

Auxiliary Carry, Parity)

Control Flags (Direction, Interrupt, Trap)

Flags - Status
 Carry (CF) – set when the result of an unsigned
arithmetic operation produces a carry.
 Overflow(OF) – set when the result of a signed
arithmetic operation is too wide to fit into the
destination.
 Sign(SF) – set when the result of an arithmetic or
logical operation generates a negative result.
 Zero(ZF) – set when the result of an arithmetic or
logical operation is zero.

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Flags – Status (cont)
 Auxiliary Carry(AF) – set when the result of an operation
causes a carry from bit 3 to bit 4.

 Parity(PF) – reflects whether the number of 1 bits in the

result of an operation is even or odd. 1 – odd, 0-even.

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Flags - Control
 Interrupt(IF) – used to allow or prohibit the interruption
of a program.

 Trap(TF) – used for single stepping through the program.

 Direction(DF) – used with string instructions.

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 Segment Registers
 There are 4 segment registers in 8086 Microprocessor and
each of them is of 16 bit. The code and instructions are stored
inside these different segments.
 Code Segment (CS) Register:
The user cannot modify the content of these registers. Only
the microprocessor's compiler can do this.
 Data Segment (DS) Register:
The user can modify the content of the data segment.
 Stack Segment (SS) Registers:
The SS is used to store the information about the memory
segment. The operations of the SS are mainly Push and
Pop.

 Extra Segment (ES) Register:

By default, the control of the compiler remains in the DS
where the user can add and modify the instructions. If
there is less space in that segment, then ES is used. ES is
also used for copying purpose.
 Pointers and Index Registers
 The pointers will always store some address or memory
location. In 8086 Microprocessor, they usually store the
offset through which the actual address is calculated.
 Instruction Pointer (IP):
The instruction pointer usually stores the address of the next
instruction that is to be executed. Apart from this, it also acts
as an offset for CS register.
 Base Pointer (BP):
The Base pointer stores the base address of the memory.
Also, it acts as an offset for Stack Segment (SS).
 Stack Pointer (SP):
The Stack Pointer Points at the current top value of the
Stack. Like the BP, it also acts as an offset to the Stack
Segment (SS).

The indexes are used with the extra segment and they
usually are used for copying the contents of a particular
block of memory to a new location.

 Source Index (SI) Register:

It stores the offset address of the source.
 Destination Index (DI) Register:
It stores the offset address of the Destination.
Bus Interface Unit
 BIU (Bus Interface Unit) sends out addresses, fetches
instructions from memory, reads data from ports and
memory, and writes data to ports and memory.

 In other words, the BIU handles all transfers of data and

addresses on the buses for the execution unit.
Pipelining

 While EU is decoding an instruction or executing an

instruction that does not require the use of buses, the
BIU pre-fetches upto six instructions bytes and stores in a
FIFO register called queue.

When the EU is ready for next instruction, it simply reads

the next instruction from the queue in the BIU , decodes
and then executes it.
 This pre-fetch and queue scheme greatly increases the
processing speed.
 The process of fetching the next instruction while the
current instruction executes is called
pipelining.
 Pipelining feature greatly speeds up processing.
Memory Segmentation
in 8086 Microprocessor
 Segmentation is the process in which the main memory
of the computer is logically divided into different
segments and each segment has its own base address.
 It is basically used to enhance the speed of execution of
the computer system, so that the processor is able to
fetch and execute the data from the memory easily and
fast.
 Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special
purpose registers (mentioned below) called as Segment
Registers.
Memory Segments &
Segment Registers
 At any given time the 8086 works with only four 65,536-
byte (64-Kbyte) segments within the 1,048,576- byte (1-
Mbyte) range.

 Four segment registers in the BIU are used to hold the

upper 16 bits of the starting addresses of four memory
segments that the 8086 is working with at a particular
time.

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 Code Segment (CS) register
 Data Segment (DS) register

 Stack Segment (SS) register

 Extra Segment (ES) register

 Code segment register (CS): is used for addressing
memory location in the code segment of the memory,
where the executable program is stored.

 Data segment register (DS): points to the data segment

of the memory where the data is stored.

 Extra Segment Register (ES): also refers to a segment in

the memory which is another data segment in the
memory.

 Stack Segment Register (SS): is used for addressing stack

segment of the memory. The stack segment is that
segment of memory which is used to store stack data.
 A segment register is used to hold the upper 16 bits of
the starting address for each segment.

 For example, the CS register holds the upper 16 bits of

the starting address for the segment from which BIU is
currently fetching instruction code bytes.
 In short,
 The CS register holds the upper 16 bits of the starting
address of the memory segment where the instruction
code bytes are stored.

 The SS register holds the upper 16 bits of the starting

address for program stack.

 The DS register and ES registers are used to hold the

upper 16 bits of the starting addresses of the two
memory segments that are used for data.
 Types Of Segmentation
 Overlapping Segment – A segment starts at a particular
address and its maximum size can go up to 64kilobytes.
But if another segment starts along with this 64kilobytes
location of the first segment, then the two are said to
be Overlapping Segment.

 Non-Overlapped Segment – A segment starts at a

particular address and its maximum size can go up to
64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two
segments are said to be Non-Overlapped Segment.
 Rules of Segmentation

Segmentation process follows some rules as follows:

 The starting address of a segment should be such that it

can be evenly divided by 16.

 Minimum size of a segment can be 16 bytes and the

maximum can be 64 kB.
 Advantages of the Segmentation

The main advantages of segmentation are as follows:

 It provides a powerful memory management mechanism.

 Data related or stack related operations can be performed

in different segments.

 Code related operation can be done in separate code

segments.

 It allows to processes to easily share data.

 It allows to extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an
addressing capability of 1 Megabytes. Without
segmentation, it would require 20 bit registers.

 It is possible to enhance the memory size of code data or

stack segments beyond 64 KB by allotting more than one
segment for each area.
Segment Base and Offset
 The BIU always insert zeros to the lowest 4 bits (Nibble)
of the 20 bit starting address for a segment.

 For example, if the code segment contains 348AH, then

the segment will start at address 348A0H.

 The part of a segment starting address stored in a

segment register is called the Segment Base.

 Offset is the displacement of the memory location

from the starting location of the segment.
 The offset registers for the different segment registers are
shown below:
Instruction Pointer
 Instruction Pointer (IP) is a 16 bit register that holds a 16
bit value called offset and it points to the memory
location from where the next instruction is to be fetched.

 After the execution of each and every instruction, the IP

register is automatically incremented by one so as to
point to the next memory location.
Calculation of Physical address of a
memory location

 The complete physical address which is 20-bits long is

generated using segment and offset registers each of the
size 16-bit.
 The content of a segment register also called as segment
address, and content of an offset register also called as
offset address.
 To get total physical address, put the lower nibble 0H to
segment address and add offset address. The figure
shows the formation of 20-bit physical address
Suppose the CS register contains 348AH, and IP register
contains 4214H respectively.

Then the BIU automatically inserts four zeros to the right of

the content of CS register to get the starting address of
the code segment.
ie; 348A0H
Then 16 bit offset value 4214H in the IP register is added
to this segment base address to get the 20 bit physical
address.
Physical address calculation

50
Contd..
CS = 2000H Base address

IP = 3000H Offset address

CS : IP
2000H : 3000H

Physical address
= 20000H +
3000H
23000H
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Pin Descriptions of 8086

 The 8086 microprocessor is a 40 pin DIP IC in which

there are 20 pins on each side of the IC.

 It requires +5 volts Dc for its operation

Pin Descriptions of 8086
Pin Descriptions of 8086
 AD0 to AD15 ( Address/Data Bus)
 These lines are multiplexed unidirectional address and
status bus. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
 A16-A19/S3-S6S6 (Address/Status Bus)
 These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries
status signals.)
 S6 is used as bus master, which handles the internal bus
control.
 S5 is used as interrupt flag.
 S4 and S3 are used to select the segment out of the four
segments.
 Status pins functions as follows:
 S6 is used as bus master, which handles the internal bus
control.
 S5 is used as interrupt flag.
 S4 and S3 are used to select the segment out of the four
segments.

 Ready
 It is available at pin 22. It is an acknowledgement signal
from I/O devices that data is transferred. It is an active
high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait
state.
 RESET
 It is available at pin 21 and is used to restart the
execution. It causes the processor to immediately
terminate its present activity. This signal is active high for
the first 4 clock cycles to RESET the microprocessor.
 INTR
 It is available at pin 18. It is an interrupt request signal,
which is sampled during the last clock cycle of each
instruction to determine if the processor considered this
as an interrupt or not.

 NMI
 It stands for non-maskable interrupt and is available at
pin 17. It is an edge triggered input, which causes an
interrupt request to the microprocessor.



 QS1 and QS0
 These are queue status signals and are available at pin 24
and 25. These signals provide the status of instruction
queue. Their conditions are shown in the following table :

QS0 QS1 Status

0 0 No operation
0 1 First byte of
opcode from the
queue
1 0 Empty the queue
1 1 Subsequent byte
from the queue
 S0, S1, S2
 These are the status signals that provide the status of
operation, which is used by the Bus Controller 8288 to
generate memory & I/O control signals. These are available at
pin 26, 27, and 28. Following is the table showing their status:
S2 S1 S0 Status
0 0 0 Interrupt
acknowledgement

0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive


Minimum mode and Maximum mode
configurations of 8086
 The 8086 microprocessor can work in two modes of
operations : Minimum mode and Maximum mode.
 In the minimum mode of operation the microprocessor
do not associate with any co-processors and can not be
used for multiprocessor systems.
 In the maximum mode the 8086 can work in multi-
processor or co-processor configuration.
 Minimum or maximum mode operations are decided by
the pin MN/ MX.
 When this pin is high 8086 operates in minimum mode
otherwise it operates in Maximum mode.
Minimum Mode
 When MN/MX’ = 1, the 8086 microprocessor runs in the
minimum mode.
 All the control signals required for memory operations
and I/O interfaces are provided by the system’s only
processor running in minimum mode, the 8086, alone.
 The circuit in this case is simple, but it does not permit
multiprocessing.
 In this mode, the microprocessor chip itself transmits all
control signals. The system’s latches, transceiver, clock
generator, memory, and I/O devices make up the
remaining parts.
Minimum mode configuration
Maximum Mode
 When 8086 is used as more than just a processor to
perform calculations, that is when 8086 is operating in
maximum mode.

 The MN/MX pin is connected to the ground to operate

the 8086 in maximum mode.

 The system’s components are identical to those in the

minimum mode system.
Maximum mode configuration
Pin assignments of Minimum Mode and Maximum
Mode (Pins 24 to 31)