Course Name: Basic Electronics Engineering

Course Code: EC1000

Dr. Situ Rani Patre

Assistant Professor
ECE, NIT Rourkela
[email protected]
Course Objective:

• To introduce Electronics Engineering in a nutshell

• To explain the role of Electronics Engineering in all other engineering disciplines
• To explain the basic building blocks of digital and analog electronic circuits
• To understand the behavior and operation of several non-linear electronic
devices: the operational amplifier, the PN junction diode, the field-effect
transistor, and the bipolar junction transistor.

2
Syllabus:
Module-I: (Analog Electronics) 10 Hrs
Part-1: Introduction to electronic Systems
Part-2: Diode circuit models and Applications: - Introduction to circuit models, Clippers and
Clampers.
Part-3: Transistors –BJT and MOSFET: - BJT construction and operation, BJT configurations, BJT
current components BJT characteristics, Transistor as an amplifier and switch, MOSFET.
Module-II: (Digital Electronics Fundamentals) 10 Hrs
Part-1: Brief on Digital Electronics: - Review of logic gates, Number systems
Part-2: Combinational Circuits: - Combinational logic (4 variables K-map), Flip flops (T, D, JK),
Counters and Registers
Part-3: Data Converters: - Digital-to-Analog Converter (DAC), Analog-to-Digital Converter (ADC).
Module-III (Special Topic in Electronics) 16 Hrs
Part-1: Operational Amplifier (Op-amp) and application: - Op-amp: Introduction, Internal Block
diagram of Op-amp, Op-amp Characteristics
Part-2: Linear operations using Op-amp:- Inverting amplifier, Non-inverting Amplifier, Voltage
follower, Summing and Difference amplifier, Integrator and Differentiator, Comparator
Part-3: Miscellaneous Electronic Devices:- SCR, LED, Photodiode, Laser, Solar Cells, Opto-Couplers.
Part-4: Sensors:- Introduction and describing sensor performance, Temperature sensors, Light sensors,
Force sensors, Displacement sensors, Motion sensors, Sound sensors, Sensor interfacing.
Part-5: Introduction to basic Communication systems/principles: Fundamentals of Analog
communication (AM, FM), Introduction to digital communication (Sampling, PAM, PCM, PPM,
PWM, Modulation and demodulation techniques ), Communication Networks, Introduction to Mobile
Communication 3
Course Outcomes:

• Design of various diode circuits

• Design a simple transistor amplifier and other circuits
• Design simple combinational and sequential circuit.
• Design circuits using ideal Op-amp to perform mathematical operations on
analog signals.
• Realize the importance of various analog and digital electronic systems, and
electronic devices.

4
Suggested Readings
1. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford University Press
2. D. A. Neamen, Microelectronics Circuit Analysis and Design, The McGraw
Hill Companies
3. Boylestad, Robert L., Louis Nashelsky, Electronic Devices and Circuit,
Pearson
4. M. M. Mano, M. D. Ciletti, Digital Design, PHI
5. S Haykin, Communication Systems, John Wiley & Sons Inc.

Suggested Video Lectures

1. Fundamentals of semiconductor devices
https://nptel.ac.in/courses/108/108/108108122/
2. Solid State Devices https://nptel.ac.in/courses/117/106/117106091/
3. Switching Circuit and Logic Design
https://nptel.ac.in/courses/106/105/106105185/
4. Analog Circuits https://nptel.ac.in/courses/117/107/117107094/
5. Principles of Communication System part 1
https://nptel.ac.in/courses/108/104/108104091/

5
Grading…..

Mid Semester Exam 30 %

TA (Assignment/Quiz/Presentation/Class performance) 20 %
End Semester Exam 50 %
Total 100 %

6
Electronic Devices

Digital Computers

7
 Applications

Home Automation Navigation Robotics

Satellite System Radar System

Medical System 8
 Electronics Circuit and Components

Analog Circuit Digital Circuit

(Analog Signal) (Digital Signal)

Diode Logic Gates

Transistor Integrated Circuits

Diode Transistor Integrated Circuits

LED Seven Segment Display LDR Sensor 9

 Electronics Circuit

Analog Circuit Digital Circuit

(Analog Signal) (Digital Signal)

Diode Logic Gates

Transistor Integrated Circuits

Difference between analog and digital signals/circuits

Analog signal have continuous Digital signal have discrete set

varying values of values

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 Mercury Thermometer Digital Thermometer

Why digital signal and digital circuits ??

Q. Why digital?
 Digital data can be processed and transmitted more efficiently and
reliably
 Storage of digital data require less space and reproduced with great
accuracy
 Noise (unwanted voltage fluctuation) does not affect digital data
compared to analog data

Data ??
Information in the form of numbers, text, audio, and video
In digital system all the data is in the form of binary number 11
 Why Binary Number
• Digital components/circuits are made up of transistors (MOS
transistors) which acts like switch: ON and OFF states
– Two states of switch → binary numbers (logic 1 and logic 0)
– Different conventions for switch ON and OFF states
• ON = 1, OFF = 0
• Low voltage = 0, high voltage = 1
• No current = 0, flow of current = 1
• No light = 0 and light = 1
• True = 1 and False = 0

http://iamtechnical.com/sites/default/files/2n
7000-mosfet-as-a-switch.gif 12
Example: Digital Computer which receives data (input data), stores and
processes it, and produces data (output data)

Data: numbers, text, audio, and video in the form of binary numbers (string
of 0s and 1s), 2 digits = 0, 1. Ex.: 1001

Bit single binary digit (0 or 1)

Nibble collection of 4 bits
Byte collection of 8 bits
Word collection of 16/32/64 bits
1 Kbyte 2^10 bytes = 1024 bytes
1 Mbyte 2^20 bytes
1 Gbyte 2^30 bytes 13
 Number System
Two categories: Weighted and non-weighted
Weighted/positional number system ??
A weight is associated to every digit position hence the digit position is
important
Ex.: Decimal number 125.25

We know the decimal number system, 10 digits = 0,1,2,3,4,5,6,7,8,9

Most used number systems:

 Decimal (10 digits: 0,1,2,3,4,5,6,7,8,9)
 Binary (2 digits: 0, 1)
 Octal (8 digits: 0,1,2,3,4,5,6,7)
 Hexadecimal (16 digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)

14
Decimal number system
10 digits = 0,1,2,3,4,5,6,7,8,9
Weighted/positional number system
A weight is associated to every digit position hence the digit position is important
Ex.: (125.25)10=base or radix
1 2 5 .2 5
weight = (r=10) no. position 102 101 100 10-1 10-2
∑ (digit×weight) 1×102 2×101 5×100 2×10-1 5×10-2
(125.25)10 100 20 5 .2 .05
----------------------------------------------------------------------------------------------------
Binary number system
(decimal representation of binary number)
2 digits = 0,1
Ex.: (101.01)2 1 0 1 .0 1
weight = (r=2) no. position 22 21 20 2-1 2-2
∑ (digit×weight) 1×22 0×21 1×20 0×2-1 1×2-2
(5.25)10 4 0 1 .0 .25

Decimal = ∑ (digitp×(weightp = r^p)) 15

Q: Compute the decimal equivalent of binary number 110101
1×25+1×24+0×23+1×22+0×21+1×20
Range of number value with n-bits 32+16+0+4+0+1 = (53)10
• With n bits, 2n distinct values can be represented
• Range: 0 to 2n-1
Ex.: n=1 bits, 2(n=1 )=2 different combinations which represent 0 & 1

n=1 bit n=2 bits n=3 bits n=4 bits

B D B D B D B D B D
0 0 00 0 000 0 0000 0 1000 8
1 1 01 1 001 1 0001 1 1001 9
21 10 2 010 2 0010 2 1010 10
11 3 011 3 0011 3 1011 11
22 100 4 0100 4 1100 12
101 5 0101 5 1101 13
Q: how many bits required 110 6 0110 6 1110 14
to represent 50
25-1=31 111 7 0111 7 1111 15
31<50<63
26-1=63 23 24
n=6
Octal, n=3 Hexadecimal, n=4 16
Binary ↔ Decimal
 Binary to decimal Q: Convert 0.45510 in to binary.
• Decimal to Binary For fractional number
Multiply fraction with 2
Ex.: (135)10 write integer left to right
Binary representation of decimal number: Integer fraction
Decimal no. is divided by 2 (radix of binary) 0.455×2 = 0 .91
write remainder Left to right
0.91×2 = 1 .82
Decimal Remainder 0.82×2 = 1 .64
135/2 1 0.64×2 = 1 .28
67/2 1 0.28×2 = 0 .56
33/2 1 0.56×2 = 1 .12
16/2 0 Left to right 0.12×2 = 0 .24
10000111
8/2 0
4/2 0 Cross check
(10000111)2
2/2 0
↕
1 (135)10 (0.455)10 ↔ (0.0111010)2
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Hexadecimal number system
16 digits = 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Ex.: (B65F)H
Decimal representation of hexadecimal number:
B 6 5 F
weight = (base=16) no. position 163 162 61 160
∑ (digit×weight) 11×163 6×162 5×161 15×160
(46687)10 45056 1536 80 15
Binary 1011 0110 0101 1111

B H D B H D
0000 0 0 1000 8 8
0001 1 1 1001 9 9
0010 2 2 1010 A 10
0011 3 3 1011 B 11
0100 4 4 1100 C 12
0101 5 5 1101 D 13
0110 6 6 1110 E 14
0111 7 7 1111 F 15 18
Base conversion
 Binary ↔ decimal
 Hexadecimal ↔ binary
 Hexadecimal ↔ decimal
 Octal to decimal and binary

Binary to Decimal Decimal to Binary

(a) (10110.0101) 2 (a) (53.1575)10
(b) (1010.1101) 2 (b) (3.1415 · · ·)10
(c) (11001010.0101)2 (c) (432)10
Octal to Decimal Decimal to Octal
(a) (26.24) 8 (a) (1984)10
(b) (1044)8 (b) (3.1415 · · ·)10
(c) (432.2)8 (c) (153.513)10
Express the following numbers in hexadecimal:
(a) (110.010)2
(c) (432)10
Express the following numbers in binary:
(a) (123.4)8
(b) (64CD)16
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 Binary Arithmetic
Binary Addition
Ex. 01111101 + 00011001 = ?
0+0=0 (Sum=0, Carry=0) 125+25=150
0+1=1 (Sum=1, Carry=0)
1+0=1 (Sum=1, Carry=0)
1+1=10 (Sum=0, Carry=1)
Ex. 10 + 11 = 101 ← Binary, Carry=1, Sum=01
2+ 3 = 5 ← Decimal

Q. Perform the binary addition of (15.25)10 and (7.5)10

Binary Subtraction
Ex. 10100101 − 1010111 = ?
0-0=0 165 − 87 = 78
0-1=1 (difference 1, borrow 1)
1-0=1
1-1=0
Ex. 1110 − 111 = 111 ← Binary, difference=111
14 − 7 = 7 ← Decimal

Q. Perform the binary subtraction of (18.75)10 − (12.5)10 20

 Approaches to represent –ve numbers
1) Signed number
2) 1’s complement
3) 2’s complement

Signed number
• MSB (most significant bit) indicates sign
• (0: +ve, 1: −ve) n=4 bits
B D B D
1 0 1 0 0000 +0 1000 −0
MSB LSB 0001 +1 1001 −1
0010 +2 1010 −2
• Drawbacks:
• Different representa on for +0 and −0 0011 +3 1011 −3
• Out of n-bits only n-1 bits indicate 0100 +4 1100 −4
magnitude 0101 +5 1101 −5
• Range of numbers: −(2n−1-1) to +(2n−1-1) 0110 +6 1110 −6
0111 +7 1111 −7
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 1’s (ones) complement
• +ve numbers are same as signed number (MSB represent sign)
• −ve numbers are represented in 1’s complement
 Complement of every bit of given number
 MSB indicate sign of the number
Ex. 1’s complement of 4 is −4
4 = 0 1 0 0 → complement → 1 0 1 1 = −4 n=4 bits

5 = 0 1 0 1 → complement → 1 0 1 0 = −5 1’s D 1’s D

complement complement

Q. Find the 1’s complement of 10100101 0000 +0 1000 −7

0001 +1 1001 −6
• Drawbacks: 0010 +2 1010 −5
o Different representa on for +0 and −0 0011 +3 1011 −4
o Out of n-bits only n-1 bits indicate magnitude 0100 +4 1100 −3
o Range of numbers: −(2n−1 −1) to +(2n−1 −1)
0101 +5 1101 −2
• Advantage:
0110 +6 1110 −1
 Subtraction can be done using addition
 Simple circuit 0111 +7 1111 −0
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 2’s (Twos) complement
• +ve numbers are same as signed number (MSB represent sign)
• −ve numbers are represented in 2’s complement
 1’s complement + 1
 MSB indicate sign of the number
Ex. 2’s complement of 4 is −4
2’s n=4 bits
1’s 2’s D 2’s D
4 = 0100 −−→ 1011 + 1 = 1100 = −4 complement complement
1’s 0000 +0 1000 −8
5 = 0101 −−→ 1010 + 1 = 1011 = −5
2’s 0001 +1 1001 −7

Q. Find the 2’s complement of 10100101 0010 +2 1010 −6

0011 +3 1011 −5
 Advantage: 0100 +4 1100 −4
 Unique representation for 0 0101 +5 1101 −3
 Range of numbers: −(2n-1) to +(2n-1 −1)
0110 +6 1110 −2
 Subtraction can be done using addition
 Simple circuit 0111 +7 1111 −1
(n represents no. of bits here 4 bits) 23
 Subtraction using 2’s complement
Ex. Compute R = A-B using 2’s complement
1. Compute 2’s complement of B (let B2 = -B)
2. Add A and B2 (R = A+ B2)
3. If a carry is obtained (extra 1 bit as MSB)
• Ignore the carry
• Result is +ve number
4. Else
• R obtained in step 2 is the result in 2’s complement
• Result is −ve number
 Most digital system use 2’s complement for representation of –ve number
Ex. Compute 7−5 using 2’s complement.
1. A=7, B=5. B2=2’s complement of B
B =5 = 0101 −−−−−−−→
1’s 1010 = B1
B2 = B1 + 1 = 1011
2. R=A+B2,
3. Carry obtained, ignore the carry
Resultant value is 2 = 0010
Q. Compute 5-7 using 2’s complement 24
 Other features of 2’s complement
1. Weighted number representation (you can cross check 2’s complement number)
7 = 0111 = +0+22+21+20 = +7
− 5 = 1011 = − 23+0+21+20 = −5
5 = 0101 −− 1’s → 1010 +1 = 1011

2’s
2. Follow this video lecture:
https://youtu.be/FG_8T1jUTVU?list=PLbRMhDVUMngfV8C6ElNAUaQQz06wEhF
M5&t=1615

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Solve the following problems:

1. Find 2’s complement of 17.

2. Find decimal equivalent of 2’s complement number 1000
3. 2’s complement representation of a 16-bit number is FFFF. Find magnitude
of its decimal equivalent.
4. Find the equivalent 6-bit 2’s complement representation of 2’s complement
number 1101
5. Find the range of signed decimal number that can be represented by 6-bit
1’s complement representation.

26
To simplify the problem of communication between human and machine, several codes
have been devised in which decimal digits are represented by sequences of binary
digits.

Binary Coded Decimal (BCD)

 10 digits of decimal are codes with 4 binary digits (nibble)
 4-bit : 24 = 16 possible combinations
 Out of 16 combinations 6 are not used (1010, 1011, 1100, 1101, 1100, 1111)
 k digit decimal requires 4k bits in BCD representation

Ex. BCD of 165 is 0001 0110 0101

BCD of 12.5 is 0001 0010. 0101

Decimal 0 1 2 3 4 5 6 7 8 9
BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

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 Excces-3
 Non-weighted binary code
Decimal BCD Excess-3
 Excess-3 : BCD + 0011 (add 3)
0 0000 0011
 Used in early computers
1 0001 0100
2 0010 0101
Ex. Excess-3 of 5 is its BCD+3
3 0011 0110
BCD of 5 = 0101
4 0100 0111
0 1 0 1 5 5 0101 1000
+ 0 0 1 1 OR + 3 6 0110 1001
1 0 0 0 8 7 0111 1010
8 1000 1011
9 1001 1100

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Recap: Number System
 Binary
 Decimal
 Hexadecimal
 Binary arithmetic: Addition, Subtraction, 1’s and 2’s complement
 BCD
 Excess-3 code
 Number system conversion

 Focused on binary numbers, why?

 The digital circuits operate on binary numbers

− One of the main objective of this subject is to understand the design of basic
circuits which operates on the binary number
− These circuits are known as logic/switching circuits

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 Logic Gate
− Logic Gates are the primary building blocks of logic/switching circuits
− Transistor with binary voltage (0 and 5 Volts) acts as switch
− Transistor are the basic building blocks of logic gates and hence digital circuits
− Logic behind the logic gates can be described using switch

Switch open:
• Current does not flows
through circuit and bulb does
not glow
• No current, No light, Logic 0

Switch closed:
• Current flows through circuit
and bulb glows
• Current, Light, Logic 1

• Input: voltage, Output: light https://learn.sparkfun.com/tutorials/trans

istors/applications-i-switches
30
Integrated Circuits (ICs) or chips contains a large number of logic gates
• Small Scale Integration (SSI) < 12 transistors/chip
• Medium Scale Integration (MSI) < 100 transistors/chips
• Large Scale Integration (LSI) < 1000s transistors/chip
• Very Large Scale Integration (VLSI) > 104 transistors/chips

31
 NOT Gate
 Also known as Inverter
 Single input, x and single output z
 z = x’ Truth Table
x z=x’
x z 0 1
1 0
NOT gate symbol

https://circuitglobe.com/wp-content/uploads/2015/12/NOT-GATE-FIG-6-compressor.jpg
https://www.allaboutcircuits.com/textbook/digital/chpt-3/dip-gate-packaging/
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 AND Gate
 AND operation is represented by dot (∙)
 Many inputs (two) x, y and single output z
 Output is 1 only when all the inputs are 1
otherwise 0
 Series connection of switches

x Switches are connected in series

z= x ∙ y http://www.technologystudent.com/images2/dig
y 3a.gif

AND gate symbol

Truth Table
x y z=x∙y
0 0 0
7408
0 1 0
1 0 0
1 1 1
AND gate IC 33
 OR Gate
 OR operation is represented by plus (+)
 Output is 0 only when all the inputs are 0
otherwise 1
 Many inputs (two) x, y and single output z
 Parallel connection of switches

x Switches are connected in parallel

z = x+y
y http://www.technologystudent.com/image
s2/dig4a.gif

OR gate symbol
Truth Table
x y z=x+y
0 0 0
0 1 1
1 0 1
https://circuitdigest.com/sites/default/files/inlineimages 1 1 1
/74LS32-Pinout.gif 34
 NAND Gate
 NAND operation is complement (inverse) of
AND operation
 Many inputs (two) x, y and single output z
 Output is 0 only when all the inputs are 1
otherwise 1
x
y https://androiderode.com/wp-
content/uploads/2013/05/NAND_animation-
androiderode1.gif
NAND gate symbol
Truth Table
x y
0 0 1
0 1 1
1 0 1
1 1 0
35
 NOR Gate
 NOR operation is complement (inverse) of OR operation
 Many inputs (two) x, y and single output z
 Output is 1 only when all the inputs are 0 otherwise 0

x
y
NOR gate symbol

Truth Table
x y
0 0 1
0 1 0
1 0 0
1 1 0
36
 Ex-OR Gate
 Exclusive OR (Ex-OR) operation is denoted by
 Many inputs (two) x, y and single output z

 Output is 0 for similar input while output is 1 for

dissimilar inputs
x
y
Ex-OR gate symbol
Truth Table
x y z=x y
0 0 0
0 1 1
1 0 1
1 1 0
37
 Ex-NOR Gate
 Exclusive NOR (Ex-NOR) operation is denoted by
 Many inputs (two) x, y and single output z

 Output is 1 for similar input while output is 0 for dissimilar inputs

x
z = x y = (x y)’
y
Ex-NOR gate symbol
Truth Table
x y
0 0 1
0 1 0
1 0 0
https://fromreadingtable.com/wp- 1 1 1
content/uploads/2017/10/XNOR-gate-IC.jpg
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 AND, OR and NOT gates are primary gates
 NAND, NOR, Ex-OR and Ex-NOR are derived from primary gates
 NAND and NOR are known as universal gates because all logic operations
can be performed through only NAND or NOR gates

39
 Boolean Algebra
Boolean Algebra: Algebraic expression of logical variables and constants
(binary digits) related by logical operators (AND, OR, NOT, …….) which define a
digital circuit.

Ex.

Here,
A, B are input variables and Out is output variable

Logic Operator Name

Ex-OR
AND
+ OR
‘ or NOT

40
http://pubs.sciepub.com/jcsa/1/1/3/image/fig3.png
Q. Draw the logic diagram and truth table to implement following
Boolean expressions:
(i) u+x+x'(u+y')
(ii) u(x z)+y'
(iii) (u y)'+x

41
Q. Write Boolean expressions, construct the truth tables and draw
timing diagram describing the outputs of the given circuits

42
Q. Write Boolean expressions, construct the truth tables and draw
timing diagram describing the outputs of the given circuits

43
 Basic Laws of Boolean Algebra
• Basic identities • Involution law

• Cumulative law

• Idempotent law
• Associative law

• Complementation law • Distributive law

44
 Basic Laws of Boolean Algebra

• Absorption law • Useful law

• Principle of duality
• Interchange AND and OR
• Interchange 0 and 1
Ex. is dual of
Ex. is dual of

Q. Simplify F = x’y+y’z’+xy+y’z
Q. Simplify F = x’y’z + xyz + x’yz + xy’z

45
 DeMorgan’s Theorem

 NOT (x AND y) = (NOT x) OR (NOT y) →

 NOT (x OR y) = (NOT x) AND (NOT y) →

Q. Simplify F = (x+y)’(x’+y’)
Q. Simplify F = (xy’+x’y)’
Q. Simplify F = (wxy’+z)’+(wx’+xy’)’
Q. Simplify F = (xyz)’(x+z)(x+z’)
Q. Find complement of xy’z+x’yz+xyz
Q. Design the logic circuit and list the truth table of the function F = xz+xy’+yz’
Q. Given two 8-bit string A = 10110101 and B = 11101001 perform following
logical operations (a) AND (b) XOR and (c) NOT A

46
 • AND and OR logic can be converted to each other with the help of NOT
• For this conversion invert inputs and outputs

Ex. Design OR logic using AND and NOT

x y x’ y’ (x’y’)’ =
x (x’)’+(y’)’ = x+y
x+y 0 0 1 1 0
y 0 1 1 0 1
1 0 0 1 1
1 1 0 0 1

Q. Implement the Boolean function: F = xy+x’y’+y’z with OR and NOT gates,

draw the logic diagram and prove by truth table
47
 Gray Codes
 Non-weighted binary code
 Gray code for successive decimal integers differ in only one digit
 Cyclic codes
 Self-reflected code
 Useful in analog-to-digital converters
 Reduced error in conversion
 Binary to Gray and Gray to binary is easy
0 0 0
Binary → Gray 0 1 1
B3 B2 B1 B0 → G3 G2 G1 G0 similar digits → 0 1 0 1
dissimilar digits → 1
G0 = B0 B1 1 1 0
G1 = B1 B2
G2 = B2 B3
G3 = B3

Q. Convert the binary 101101 to Gray

48
Decimal Binary Gray
0 0000 0000
One bit change
1 0001 0001
One bit change
2 0010 0011
3 0011 0010 • Across successive codes only one bit
4 0100 0110 change the state → Cyclic code
5 0101 0111 Gray → Binary
6 0110 0101 G3 G2 G1 G0 → B3 B2 B1 B0
7 0111 0100 B3 = G 3
8 1000 1100 B2 = B3 G2 Q. Convert the Gray
9 1001 1101 B1 = B2 G1 01011001 to binary
10 1010 1111
B0 = B1 G0
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000 https://blogmedia.testbook.com/blog/wp-
49
content/uploads/2015/11/Conversion-from-Gray-Code-to-Binary-Code.png
 2-bit 3-bit 4-bit
00 0 00 0 000
01 0 01 0 001
Illustration of self-reflection 11 0 11 0 011
property of Gray code 10 0 10 0 010
1 10 0 110
1 11 0 111
1 01 0 101
1 00 0 100
1 100
1 101
1 111
1 110
1 010
1 011
1 001
1 000 50
 NAND and NOR Implementation
 The NAND/NOR gate → universal gate because any logic circuit can be
implemented with it
 Digital circuits → constructed with NAND or NOR gates rather than with AND
and OR gates
 A convenient way to implement a Boolean function with NAND/NOR gates is
to obtain the simplified Boolean function in terms of Boolean operators and
then convert the function to NAND/NOR logic.
 NAND and NOR are dual of each other → DeMorgan’s Theorem

(xyz)’ = x’+y’+z’

(x+y+z)’ = x’y’z’

51
 NAND implementation of different logic gate

NOT (Inverter)

AND

OR

NOR

52
Implementation of Boolean functions with NAND gates requires that the
functions be in sum-of-products form

53
Ex. F = AB+CD → SOP

AND-OR Realization

NAND-OR Realization NAND-NAND Realization

F = ((AB)’)’+((CD)’)’ = AB+CD F = ((AB)’(CD)’)’ = ((AB)’)’+((CD)’)’
= AB+CD 54
i) F = xy’+x’y+z → SOP

z’ F = xy’+x’y+z F = ((xy’)’(x’y)’z’)’
= xy’+x’y+z

ii) F = A(CD+B)+BC’
CD
CD+B
(CD+B)A

BC’
F = A(CD+B)+BC’

(CD)’
CD+BC’
((CD+BC’)A)’

(BC’)’
F = (CD+BC’)A+BC’55
iii) F = (AB’+A’B)(C+D’)

AB’
AB’+A’B
A’B

C+D’ F= (AB’+A’B)(C+D’)

(AB’)’
AB’+A’B
(A’B)’

C+D’ F= (AB’+A’B)(C+D’)

56
iv) Ex-OR using NAND gate, F = x y = xy’+x’y

xy’

= xy’+x’y

x’y

((xy)’x)’ = (xy+x’) = x’+y

(xy)’ = ((x’+y)(x+y’))’
= (x’+y)’+(x+y’)’ = xy’+x’y
((xy)’y)’ = (xy+y’) = x+y’

4 NAND gates are required for the design of Ex-OR using NAND gate
57
NOR implementation of different logic gate
Implementation of Boolean functions with NOR gates requires that the
functions be in product-of-sum (POS) form

(x+y+z)’ = x’y’z’
i) F = (A+B)(C+D)E ← POS

(A+B)’ AND with inverted inputs = NOR

= (A+B)(C+D)E

E’

ii) F = (AB’+A’B)(C+D’) ← POS

AB’
(AB’+A’B)’
= (AB’+A’B)(C+D’)
A’B

(C+D’)’
 Minterm and Maxterm
Literals: logic variable in uncomplemented or complemented form
Ex. x, x’, y, y’ in any Boolean expression (switching function)
For an n-variable Boolean expression, F(x1,x2,x3……xn)
Minterm: Product term (AND operation) of all the n literal
either uncomplemented → 1 or complemented → 0
Ex. x1x2x3……xn
Maxterm: Sum term (OR operation) of all the n literals
either uncomplemented → 0 or complemented → 1
Ex. x1+x2+x3+……+xn
Minterms Maxterms
Ex. Two variable (x and y) has 22 (Product Terms) (Sum Terms)
possible minterms/maxterms 0 0 x’y’ m0 0 0 x+y M0
 Each minterm is complement 0 1 x’y m1 0 1 x+y’ M1
to corresponding maxterms
1 0 xy’ m2 1 0 x’+y M2
and vice-versa.
1 1 xy m3 1 1 x’+y’ M3

 Any Boolean expression can be expressed either as sum of minterms (i.e., sum of product, SOP) or
as product of maxterms (i.e., product of sum, POS) → Canonical forms/ unique representa on 62
 Sum of Minterm/Sum of Products (SOP)

AND-OR realization

S(x,y,z) = x y z
= (x’y+xy’) z
= x’y’z + x’yz’ + xy’z’ + xyz
= 001 + 010 +100 +111 Truth Table
= m1 + m2 + m4 +m7
x y z minterm
m S
= ∑m(1,2,4,7)
= ∑(1,2,4,7) 0 0 0 x’y’z’ 0 0
0 0 1 x’y’z 1 1
0 1 0 x’yz’ 2 1
0 1 1 x’yz 3 0
1 0 0 xy’z’ 4 1
1 0 1 xy’z 5 0
1 1 0 xyz’ 6 0
1 1 1 xyz 7 1
63
 Product of Maxterm/Product of sum

OR-AND realization

S(x,y,z) = (x+y+z).(x+y’+z’).(x’+y+z’).(x’+y’+z)
= (0+0+0).(0+1+1).(1+0+1).(1+1+0)
Truth Table = M0∙M3∙M5∙M6
M x y z S = ∏M(0,3,5,6)
= ∏(0,3,5,6)
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1
65
 Each minterm is complement to corresponding maxterms and vice-versa.
m’ = M

SOP: S= ∑(1,2,4,7)
Complement
S’= ∑(0,3,5,6) = m0 + m3 + m5 +m6 = x’y’z’+x’yz+xy’z+xyz’

POS: S = ∏(0,3,5,6)

Q1 Find complement of F(w,x,y,z)= ∑(0,1,3,8,9,13,15) in sum-of-minterm form.

Q2 Convert following to the other canonical form:
(a) F(x,y,z) = ∑(1,2,4,5) (b) F(A,B,C,D) = ∏(0,1,3,4,7,11)
Q3 Convert following expressions into SOP and POS form:
(a) (w+xy’)(x+y’z) (b) xy+(w’+y’z’)(z’+x’y’)
67
 Karnaugh map or K-map
 Minimized (simplest) Boolean Expression and circuit can be determined
using K-map for given SOP and POS
• Simplest: minimum number of terms with least possible literals which
leads the circuit design using minimum number of gates
 Graphical/Pictorial representation of a Boolean expression

Variables: 2
Variables: 3
Minterms: 4
Minterms: 8
Variables: 4
Source: Digital Design, pp. 74- , Morris Mano Minterms: 16 70
 Two variables K-map

Truth Table Truth Table

x y F x y F
0 0 0 0 0 1
0 1 0 0 1 1
1 0 0 1 0 0
1 1 1 1 1 0
F = xy F = x’

Truth Table Truth Table

x y F x y F
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 F = x+y 1 1 1 F = xy+x’y’
71
 Three variables K-map
i) F(x,y,z) = ∑(0,1,6,7)
ii) F(x,y,z) = ∑(0,2,3,7)

x
y
Ex-NOR gate

F(x,y,z) = x’y’+xy = (x y)’

F(x,y,z) = x’z’+yz

iv) F(x,y,z) = ∑(1,3,5,7) iii) F(x,y,z) = ∑(0,2,3,4,6)

F(x,y,z) = z’+x’y
F(x,y,z) = z 72
Four variables K-map

i) F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14)

F(w,x,y,z) = y’+w’z’+xz’

73
ii) F(w,x,y,z) = ∑(4,5,8,12,13,14,15)

iii) F(w,x,y,z) = ∑(1,5,6,7,11,12,13,15)

F(w,x,y,z) = wx+xy’+wy’z’

F(w,x,y,z) = xz+wxy’+w’xy+w’y’z+wyz
74
iv) F(w,x,y,z) = ∑(5,6,9,10)

F(w,x,y,z) =w’xy’z+w’xyz’+wx’y’z+wx’yz’

75
 v) F(w,x,y,z) = ∑(0,4,5,7,8,9,13,15)

F(w,x,y,z) =xz+w’y’z’+wx’y’ F(w,x,y,z) =xz+x’y’z’+w’xy’+wy’z

Draw logic diagram (AND-OR realization) for the expression F

76
 Don’t care condition in K-map
• Some input variable combinations are not allowed in some situations
• Ex. BCD code converter - Out of 16 possible combinations six: 1010, 1011, 1100,
1101, 1110, 1111 are not used
• These unused input states does not affect output of BCD converter
• Output of these inputs can be considered as don’t care terms represented by X
• Don’t care term can considered as 0 or 1
• Don’t care term present in K-map can be used to form pair of 1’s or 0’s if
required

i. Simplify the Boolean function

F(w,x,y,z)=∑(1,3,7,11,15) which has don’t
care conditions, d(w,x,y,z)=∑(0,2,5)

F(w,x,y,z) = w’x’+yz

F(w,x,y,z) = w’z+yz

78
ii) The segment a of seven segment
display is activated for the digits
0,2,3,5,6,7,8,9. Derive SOP
expression for segment a

SOP for segment a

F(w,x,y,z) = ∑(0,2,3,5,6,7,8,9)
d(w,x,y,z) = ∑(10,11,12,13,14,15)
F(w,x,y,z) = w+y+xz+x’z’

79
 iii) Design BCD to Excess-3 converter

Decimal Binary Excess-3

wxyz F3 F 2 F 1 F0
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000 F0 (w,x,y,z) = z’ F1 (w,x,y,z) = y’z’+yz
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

F0 (w,x,y,z) = ∑(0,2,4,6,8)
F1 (w,x,y,z) = ∑(0,3,4,7,8)
F2 (w,x,y,z) = ∑(1,2,3,4,9)
F4 (w,x,y,z) = ∑(5,6,7,8,9) F2 (w,x,y,z) = xy’z’+x’z+x’y F3 (w,x,y,z) = w+xy+xz
d(w,x,y,z) = ∑d(10,11,12,13,14,15) 80
Design BCD to Excess-3 converter

F0 (w,x,y,z) = z’

F1 (w,x,y,z) = y’z’+yz

F2 (w,x,y,z) = xy’z’+x’z+x’y

F3 (w,x,y,z) = w+xy+xz

81
 POS simplification using K-map Truth Table
wxyz m F F’
i) F(w,x,y,z) = ∑(0,1,2,5,8,9,10)
0000 m0 1 0
Method 1: using complemented minterms
0001 m1 1 0
F’(w,x,y,z) = ∑(3,4,6,7,11,12,13,14,15)
0010 m2 1 0
0011 m3 0 1
0100 m4 0 1
0101 m5 1 0
0110 m6 0 1
0111 m7 0 1
1000 m8 1 0
1001 m9 1 0
1010 m10 1 0
1011 m11 0 1
1100 m12 0 1
F’(w,x,y,z) = wx +yz+xz’
Take complement 1101 m13 0 1
(F’(w,x,y,z))’ = (wx+yz+xz’)’ 1110 m14 0 1
F(w,x,y,z) = (w’+x’)(y’+z’)(x’+z) 1111 m15 0 182
 POS simplification using K-map Truth Table
wxyz Maxterm M F
i) F(w,x,y,z) = ∑(0,1,2,5,8,9,10)
0000 w+x+y+z M0 1
Method 2: using maxterms
0001 w+x+y+z’ M1 1
F(w,x,y,z) = ∏(3,4,6,7,11,12,13,14,15)
0010 w+x+y’+z M2 1
0011 w+x+y’+z’ M3 0
0100 w+x’+y+z M4 0
0101 w+x’+y+z’ M5 1
0110 w+x’+y’+z M6 0
0111 w+x’+y’+z’ M7 0
1000 w’+x+y+z M8 1
1001 w’+x+y+z’ M9 1
1010 w’+x+y’+z M10 1
1011 w’+x+y’+z’ M11 0
1100 w’+x’+y+z M12 0
F(w,x,y,z) = (w’+x’)(y’+z’)(x’+z)
1101 w’+x’+y+z’ M13 0

Draw the logic diagram (OR-AND realization) for it 1110 w’+x’+y’+z M14 0
1111 w’+x’+y’+z’ M15 0
ii) F(w,x,y,z) = ∏(1,4,5,6,11,12,13,14,15)

F(w,x,y,z) =(w’+x’)(x’+z)(w+y+z’)(w’+y’+z’)

84
iii) F(w,x,y,z) = ∏(0,1,2,3,4,7,8,11,12,13,14,15)

F(w,x,y,z) =(w+x)(w’+x’)(y+z)(y’+z’)

Note: Refer Book: Digital Fundamental by Thomas L Floyd for more details 85
 POS simplification using K-map Truth Table
wxyz m F F’
i) F(w,x,y,z) = ∑(0,1,2,5,8,9,10)
0000 m0 1 0
Method 1: using complemented minterms
0001 m1 1 0
F’(w,x,y,z) = ∑(3,4,6,7,11,12,13,14,15)
0010 m2 1 0
0011 m3 0 1
0100 m4 0 1
0101 m5 1 0
0110 m6 0 1
0111 m7 0 1
1000 m8 1 0
1001 m9 1 0
1010 m10 1 0
1011 m11 0 1
1100 m12 0 1
F’(w,x,y,z) = wx +yz+xz’
Take complement 1101 m13 0 1
(F’(w,x,y,z))’ = (wx+yz+xz’)’ 1110 m14 0 1
F(w,x,y,z) = (w’+x’)(y’+z’)(x’+z) 1111 m15 0 182
 POS simplification using K-map Truth Table
wxyz Maxterm M F
i) F(w,x,y,z) = ∑(0,1,2,5,8,9,10)
0000 w+x+y+z M0 1
Method 2: using maxterms
0001 w+x+y+z’ M1 1
F(w,x,y,z) = ∏(3,4,6,7,11,12,13,14,15)
0010 w+x+y’+z M2 1
0011 w+x+y’+z’ M3 0
0100 w+x’+y+z M4 0
0101 w+x’+y+z’ M5 1
0110 w+x’+y’+z M6 0
0111 w+x’+y’+z’ M7 0
1000 w’+x+y+z M8 1
1001 w’+x+y+z’ M9 1
1010 w’+x+y’+z M10 1
1011 w’+x+y’+z’ M11 0
1100 w’+x’+y+z M12 0
F(w,x,y,z) = (w’+x’)(y’+z’)(x’+z)
1101 w’+x’+y+z’ M13 0

Draw the logic diagram (OR-AND realization) for it 1110 w’+x’+y’+z M14 0
1111 w’+x’+y’+z’ M15 0
ii) F(w,x,y,z) = ∏(1,4,5,6,11,12,13,14,15)

F(w,x,y,z) =(w’+x’)(x’+z)(w+y+z’)(w’+y’+z’)

84
iii) F(w,x,y,z) = ∏(0,1,2,3,4,7,8,11,12,13,14,15)

F(w,x,y,z) =(w+x)(w’+x’)(y+z)(y’+z’)

Note: Refer Book: Digital Fundamental by Thomas L Floyd for more details 85
 Combinational Circuits

• It consists of logic gates whose outputs at any time depends only on the present
combination of inputs → no feedback paths or memory elements
Feedback path is a connection from the output of a gate to the input of
same/previous gate
• Its operation can be specified logically by a set of Boolean functions → Each
output variable is logical function of input variables

Ex.: Adder, Subtractor, Code converters, Decoder, Encoder, Multiplexer,

Demultiplexer
 Half-Adder
 Half-adder circuit performs the addition of two binary digits (bits)
 Two input variables (x,y) designated as augend and addend bits
 Two output variables designated as sum, S and carry, C

x Truth Table
S
Inputs HA Outputs m x+y C S
y C 0 0+0 0 0
1 0+1 0 1
S(x,y) = ∑(1,2) = 01+10 = x’y+xy’ = x y 2 1+0 0 1
C(x,y) = ∑(3) = 11 = xy 3 1+1 1 0
 NAND implementation of Half-Adder

x
S
y

C
https://i.stack.imgur.com/kkyLj.png

 Half-adder does not work properly when carry is 0 1

generated from previous bit addition 0 1 x
Ex. 01+11 1 1 y
01+11 = 010 ← wrong
1 0 S
 To perform proper binary addition we need three bit adder
 Full-Adder
 Full adder circuit performs the addition of three bits (two significant bits and a
previous carry)
 It consists of three inputs (two significant bits x, y and a previous carry z) and
two outputs sum, S and carry, C
Truth table
x S m x+y+z C S
Inputs y FA Outputs 0 0+0+0 0 0
z C 1 0+0+1 0 1
2 0+1+0 0 1
Ex. 01+11
3 0+1+1 1 0
1 1 z 4 1+0+0 0 1
01+11 = 100 ← correct
0 1 x 5 1+0+1 1 0
1 1 y 6 1+1+0 1 0
S(x,y,z) = ∑(1,2,4,7) 0 0 S 7 1+1+1 1 1
C(x,y,z) = ∑(3,5,6,7)
Expression and AND-OR circuit implementation of Sum and Carry

S(x,y,z) = ∑(1,2,4,7)
= x’y’z+x’yz’+xy’z’+xyz C(x,y,z) = ∑(3,5,6,7)
=x y z = xy+xz+yz
 Implementation of full adder with two half adders and an OR gate

 HA adds two bits and FA adds three bits

 Addition of two n-bit numbers → n FA or one-HA and n-1 FA
 Decoder
 It is a combinational circuit with n inputs and at most 2n outputs.
 For every input combination, only one output value will be equal to 1.
Applications:
 It can direct input data to a specified output line, for example: selection of
memory location, where input data are to be stored in (or read from) a
specified memory location.
 It can be used for implementing arbitrary switching functions as well as
some code conversions

D1
A
D2
Inputs 2×4
B Decoder Outputs
D3
D4
 2×4 Decoder
 n = 2, input lines (A and B)
 2n = 4, output lines (D0, D1, D2, D3)
 Every input combination activates single output line

A B

Truth Table
m A B D0 D1 D2 D3 D0 = A’B’
0 0 0 1 0 0 0
D1 = A’B
1 0 1 0 1 0 0
2 1 0 0 0 1 0 D2 = AB’
3 1 1 0 0 0 1
D3 = AB
 3×8 Decoder

 n = 3, input lines (x, y and z)

 2n = 8, output lines (D1 to D7)
 Every input combination activates
single output line

Truth Table
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3 × 8 decoder using two 2 × 4 decoders and an enable input

• MSB = x → Enable input

• When x = 0: upper decoder is enabled
• When x = 1: lower decoder is enabled
y
z
x
MSB
Truth Table
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 https://encrypted-
tbn0.gstatic.com/images?q=tbn:ANd9GcSMm
0 1 0 0 0 1 0 0 0 0 0 yjkBkBYo1tyWSCPvudZPcmmFtfmIg875iQobiE
Zibm52_9ZXg
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
4 × 16 decoder using two 3 × 8 decoders and en enable input w xyz Output
line
• MSB = w → Enable input 0 000 D0
• When w = 0: upper decoder is enabled 0 001 D1
• When w = 1: lower decoder is enabled 0 010 D2
0 011 D3
0 100 D4
0 101 D5
0 110 D6
0 111 D7
1 000 D8
1 001 D9
1 010 D10
1 011 D11
1 100 D12
1 101 D13
1 110 D14
1 111 D15
 Implementation of a full adder with a decoder
• A decoder provides the 2n minterms of n input variables
• Any Boolean function can be expressed in sum-of-minterms form
• Decoder, together with an external OR gate can be used to implement the
desired function.

Implementation of a full adder with a decoder

S(x,y,z) = ∑(1,2,4,7) = D1+D2+D4+D7

C(x,y,z) = ∑(3,5,6,7) = D3+D5+D6+D7

Ex.
x=1, y=0, z=1
D5 = 1, other output lines are in
logic low (i.e., 0)
S= D1+D2+D4+D7 = 0+0+0+0 = 0
C=D3+D5+D6+D7 = 0+1+0+0 = 1
 Encoder
 An encoder has 2n input lines and n output lines.
 The output lines generate the binary code corresponding to the input value.
 The encoder can be implemented with OR gates.

Octal-to-Binary Encoder: Truth Table D0

Input Output D1 LSB
D2 z
m D0 D1 D2 D3 D4 D5 D6 D7 x y z D3
D4 y
0 1 0 0 0 0 0 0 0 0 0 0
D5 x
1 0 1 0 0 0 0 0 0 0 0 1 D6 MSB
D7
2 0 0 1 0 0 0 0 0 0 1 0
3 0 0 0 1 0 0 0 0 0 1 1
4 0 0 0 0 1 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 1 0 1
6 0 0 0 0 0 0 1 0 1 1 0
7 0 0 0 0 0 0 0 1 1 1 1
 Multiplexer (MUX) or Data Selector
• A multiplexer (MUX) is a combinational circuit that selects information from one
of many input lines and directs it to a single output line.
• Selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
• It acts like an electronic switch that selects one of many sources
• It is an essential electronic component in signal routing, data communications
and data bus control applications
• Parallel to serial converter: parallel data can be transmitted in serial form via a
single data link such as a fiber-optic cable or telephone line. The advantage is
that only one serial data line is required instead of multiple parallel data lines.

2 o 1 MUX: Block diagram and logic diagram

 A four-to-one-line multiplexer

• Four input lines (I0I1I2I3)

S1’S0’I0
• Two selection lines (S0S1)
• One output line (Y)
S1’S0I1

S1S0’I2

S1 S 0 I 3
Boolean Function Implementation
The individual minterms can be selected by the data inputs, thereby providing a
method of implementing a Boolean function of n variables with a multiplexer that
has n selection inputs and 2n data inputs, one for each minterm.

F (x, y, z) = ∑(1, 2, 6, 7)
F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
 De-Multiplexer (DeMUX) or Data Distributor
• A demultiplexer (DEMUX) basically reverses the multiplexing function.
• It takes information from one line and distributes it to a given number of output
lines.
• Serial to parallel converter
• Decoders can also be used as demultiplexers
 Sequential Circuits

• Its output depend not only on present input but also on past history of the
circuit.
• Its behavior is specified by a time sequence of inputs, outputs, and past history
• Ex. Latch, Flip-Flop, Counter

Present input → combinational circuit

Past history → storage elements and feedback path
Storage elements (memory)
o It can store binary information (0 and 1)
o Fundamental storage element is latch (it can store one bit)
o Most basic form of sequential circuits
o Implemented using logic gates

Two basic memory elements:

1. Latch → operates with signal levels (known as level sensitive device)
2. Flip-Flop → operates by a clock transition i.e. 0 to 1 or 1 to 0 (known as
edge sensitive device)
 SR (Set-Reset) Latch with NOR gates
 The SR latch is a circuit with two cross-coupled NOR gates and two inputs
labeled S for set and R for reset.
 Output of each gate is connected to an input of the opposite gate. This
produces the regenerative feedback

S=1 and R=0 S=0 and R=1 S=0 and R=0

Q’ = (S+Q)’ = (1+Q)’ = 0 Q = (R+Q’)’ = (1+Q’)’ = 0 check previous state (Q,Q’)
Q = (R+Q’)’ = (0+0)’ = 1 Q’ = (S+Q)’ = (0+0)’ = 1 Q = (R+Q’)’ = (0+Q’)’ = Q
Latch is in Set state (Q=1) Latch is in Reset state (Q=0) Q’ = (S+Q)’ = (0+Q)’ = Q’
Irrespective of previous state Irrespective of previous state Latch is in previous state

S=1 and R=1: Q’ = (S+Q)’ = (1+Q)’ = 0 and Q = (R+Q’)’ = (1+Q’)’ = 0 → Invalid (not allowed)
 Active high-input SR latch

1. S=1 and R=0 → Latch is in Set state (Q=1)

Q’ = (S+Q)’ = (1+Q)’ = 0 Function Table
Q = (R+Q’)’ = (0+0)’ = 1
Input Output
2. S=0 and R=1 → Latch is in Reset state (Q=0)
Q = (R+Q’)’ = (1+Q’)’ = 0 S R Q Q’
Q’ = (S+Q)’ = (0+0)’ = 1 1 0 1 0
3. S=0 and R=0 → Latch is in previous state
0 1 0 1
Q = (R+Q’)’ = (0+Q’)’ = Q
Q’ = (S+Q)’ = (0+Q)’ = Q’ 0 0 Previous
4. S=1 and R=1 → Invalid (not allowed) 1 1 Forbidden
Q’ = (S+Q)’ = (1+Q)’ = 0
Q = (R+Q’)’ = (1+Q’)’ = 0
unpredictable or undefined state or a metastable state
Why S = R = 1 is an invalid combination

In practice, the propagation delay of two gates can not be same

Suppose, S =R = 1
It sets the output Q = Q’ = 0
Next apply S = R = 0 ← inputs, Q = Q’ = 0 ← previous state
Suppose top gate is slightly faster than bottom gate
Q=1
Q’ = (S+Q)’ = (0+1)’ = 0
For inputs S = R = 0, the next state should remain unchanged, but it is setting 1 in the latch.
Similarly, if bottom gate is slightly faster than top gate
Q’ = 1
Q = (R+Q’)’ = (0+1)’ = 0
For inputs S = R = 0, the next state should remain unchanged, but it is storing 0 in the latch.

This phenomena is known as Race Condition

One way to eliminate the invalid (race) condition in the SR latch is to ensure that inputs S
and R are never equal to 1 at the same time → D latch
 D Latch (Transparent Latch)

• It eliminates the invalid condition that occurs in SR

• It ensures that inputs S and R are never equal to 1 at the same time
• It has only two inputs: D (data) and En (enable)
• As long as the enable input is at 0, the cross-coupled SR latch has both inputs
at the 1 level and the circuit cannot change state regardless of the value of D
When En = 1
o D = 0, output Q goes to 0, placing the circuit in the reset state
o D = 1, the Q output goes to 1, placing the circuit in the set state
• Data input of the D latch is transferred to the Q output when the enable input
is ac ve → transparent latch
Graphic symbols for latches

Latch with enable input or clock: level sensitive i.e., if the enable input is active
(En=1), the output is will change depending on the R and S inputs.

Source: M. B. Patil, www.ee.iitb.ac.in/~sequel

FLIP-FLOPS

• Extension of latch
• Operates by a clock transition i.e. the output can change only at the active
clock edge (i.e., CLK transition from 0 to 1 or from 1 to 0)
• Also known as edge sensitive or edge triggered device
 SR Flip-Flop
Graphic symbols for edge triggered SR flip-flop:

Characteristics Table
for +ve edge (↑) triggered F/F
CLK S R Q Q’
0/1 X X Q Q’ No change
↑ 0 0 Q Q’ No change
↑ 0 1 0 0 Store 0
↑ 1 0 1 0 Store 1
↑ 1 1 X X Invalid
State Table for SR Flip-Flop
Q(t) S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1 State Equation:
1 0 1 0
Q(t+1) = S + R’ Q(t)
1 1 0 1
1 1 1 X
 D Flip-Flop

Graphic symbols

Characteristics Table
for +ve edge (↑) triggered F/F
CLK D Q Q’
0/1 X Q Q’ No change
↑ 0 0 1 Store 0
↑ 1 1 0 Store 1

Characteristics Equation:
Q(t+1) = D
 JK Flip-Flop

Graphic symbols S

https://electronicsforu.com/wp-contents/uploads/2017/08/JK-Flip-Flop-
800x444.png

Characteristics Table
for +ve edge (↑) triggered F/F
CLK J K Q Q’
0/1 X X Q Q’ No change
↑ 0 0 Q Q’ No change
↑ 0 1 0 1 Store 0
↑ 1 0 1 0 Store 1
↑ 1 1 Q’ Q Toggle
o When CLK = 0, R =S =1, and the RS latch holds the previous Q. In other words, nothing
happens (No change) as long as CLK=0
o When CLK=1:
• J =K =0 R =S =1, RS latch holds previous state, Q(t+1) = Q(t) i.e., No change
• J =0; K =1 R =1, S =Q’
Case (i): Q(t) =0, S =1 (i.e., R =S =1) → Q(t+1) = Q(t) = 0
Case (ii): Q(t) =1, S =0 (i.e., R =1, S =0) → Q(t+1) = 0
In either case, Q(t+1) =0, for J =0, K =1 i.e., Reset (store 0)
• J =1, K =0, S =1, R =Q
Case (i): Q(t) =0, R =0 (i.e., R =0, S =1) → Q(t+1) =1
Case (ii): Q(t) =1, R =1 (i.e., R =1, S =1) → Q(t+1) =Q(t) =1
In either case, Q(t+1) =1, for J =1, K =0 i.e., Set (store 1)
• J =1, K =1, R =Q, S =Q’. Characteristics Table
Case (i): Q(t) =0, R =0, S =1, Q(t+1) =1 for +ve edge (↑) triggered F/F
Case (ii): Q(t) =1, R =1, S =0, Q(t+1) =0
CLK J K Q (t+1)
For J = 1, K = 1, Q(t+1) =Q’(t) i.e., Complement/toggle
0/1 X X Q (t): No change
R ↑ 0 0 Q(t): No change
↑ 0 1 0: Store 0
↑ 1 0 1: Store 1
S ↑ 1 1 Q’: Toggle
State Table for JK Flip-Flop
Q(t) J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
Characteristics Equation:
1 0 1 0
Q(t+1) = K’ Q(t) + J Q’(t)
1 1 0 1
1 1 1 0
 T Flip-Flop

Characteristics Table
for +ve edge (↑) triggered F/F
CLK T Q Q’
0/1 X Q Q’ No change
↑ 0 Q Q’ No change
↑ 1 Q’ Q Toggle

Characteristics Equation:
Q(t+1) = T Q(t)
Applications of Flip-Flop: Frequency divider

Frequency divider (f/2) Frequency divider (f/2)

using D flip-flop using JK flip-flop
 Applications of Flip-Flop: Register
• A register is a group of flip-flops
• Each flip-flop is synchronized by a common clock
• Each flip-flop can store one bit of information
• An n -bit register consists of a group of n flip-flops capable of storing n bits of
binary information.

Ex. 4-bit serial input serial output (SISO) register

 Applications of Flip-Flop: Counter
• A counter is essentially a register that goes through a predetermined
sequence of binary states.
• Counters are available in two categories: ripple or asynchronous counters and
synchronous counters.
• In a ripple counter, a flip-flop output transition serves as a source for triggering
other flip-flops. Output of one flip-flop is applied to clock input of next flip-
flop.
• In a synchronous counter, the clock inputs of all flip-flops receive the common
clock.
Ripple Counter
• Asynchronous counter
• A ripple counter is an
asynchronous sequential
circuit
• A flip-flop output transition
serves as a source for
triggering other flip-flops.
• Clock ripples from one to
next flip-flop 2-bit binary counter

Ex. Binary counter

• A binary counter follows the
binary number sequence
• An n-bit binary counter
consists of n flip-flops and
can count in binary from 0
through 2n - 1.
3-bit binary counter
binary sequence: 000, 001, 010, 011, 100, 101, 110, and 111
Up-counter: observe output Q
Down-counter: observe Q’
LSB

MSB
Ripple Counter with unused states
Ex. BCD counter : counts 0-9
• All flip-flops will be in clear status when count reaches 1010 = Q3Q2Q1Q0
• Q3Q1 = 11 is applied to input of additional NAND gate
• NAND gate generates 0 which is applied to clear (reset) input of all flip-flops
• Counter terminates the count at 1010 state and reset to 0000 state
Ring Counter
• Synchronous sequential circuit
• A ring counter is a circular shift register with only one flip-flop being set at any
particular time; all others are cleared.
• The single bit is shifted from one flip-flop to the next to produce the sequence
of timing signals.
• A k -bit ring counter circulates a single bit among the flip-flops to provide k
distinguishable states.
• Initial state = 1000
• State transi on: 1000→ 0100 → 0010 → 0001 → 1000 …

Modulo-4 (Mod 4) counter https://www.electronics-tutorials.ws/wp-

content/uploads/2018/05/sequential-seq37.gif
Twisted pair or Johnson Counter

Modulo-8 (Mod 8) counter

• Johnson counter is also a circular shift

register with the complemented
output of the last flip-flop connected to
the input of the first flip-flop.
• Number of states = double of number
of flip-flop (2k)
• Initial state = 0000
108
109
110
111
112
113
114
115
116
117
118
119
 Difference amplifier
• A difference amplifier is one that responds to the difference between the two
signals applied at its input and ideally rejects signals that are common to the two
inputs.
• Although ideally the difference amplifier will amplify only the differential input
signal vId and reject completely the common-mode input signal vIcm, practical
circuits will have an output voltage vO given by

where Ad denotes the amplifier differential gain and Acm denotes its common-
mode gain (ideally zero).

• The efficacy of a differential amplifier is measured by the degree of its

rejection of common-mode signals in preference to differential signals.
• This is usually quantified by a measure known as the common-mode
rejection ratio (CMRR), defined as

120
Input signals to a differential
amplifier in terms of their
differential and common-mode
components.

A difference amplifier circuit

121
Application of superposition to the analysis of the circuit

with input vI 2 = 0,
currents in R3 and R4 are 0;
therefore, v2a = 0.
The resulting circuit is the inverting amplifier.

122
with vI 1 = 0
R3 and R4 form a voltage divider.
Therefore,

From the virtual short concept, v1b = v2b and the circuit becomes a noninverting
amplifier, for which

123
Since the net output voltage is the sum of the individual terms, we have

A property of the ideal difference amplifier is that the output voltage is zero
when vI 1 = vI 2, this condition is met if

The output voltage is then

which indicates that this amplifier has a differential gain of Ad = R2/R1

124
125
126
127
 Difference between Electrical and Electronics

• Electrical and electronic engineering may sound similar, but they

are very different.
• Both involve moving electricity around a circuit to power useful
products and machines, but that is where the similarity ends
https://youtu.be/3b41qF8gj78

• Experimental demonstration by Prof HC Verma (Course: Physics

of Semiconductor) for finding electrical conducting material
https://youtu.be/JUwng95mWqk?t=29

12
 Energy band diagram of materials

Eg » kT
Eg ≈ kT

k: Boltzmann's constant and T: Temperature in oK

kT = 0.026 eV ≈ 26 mV @ room temperature (T= 300oK)
For insulator, the energy gap Eg » kT of the order of hundreds of kT
For semiconductor Eg ≈ kT of the order of tens of kT and it behaves as
conductor @ room temperature hence the name SEMICONDUCTOR
Eg (insulator) >> Eg (semiconductor) 13
Resistivity (ρ) of Typical Materials
• Conductors
Copper: 1.7 x 10-6 Ω-cm (or 1.7 x 10-8 Ω-m)
Aluminum: 2.8 x 10-6 Ω-cm
• Insulators
SiO2: 1018 Ω-cm
• Semiconductor
Silicon: 10-3 to 103 Ω-cm
 A wide range of resistivity,
 Can be controlled by “doping” of impurities or electrical bias

(conductor) << (semiconductor) << (insulator)

OR
(conductor) >> (semiconductor) >> (insulator)

Most electronic devices are fabricated by using semiconductor materials

along with conductors and insulators.
14
 Mostly used semiconductor materials

Silicon (Si) Germanium (Ge)

Electronic Number: 14 Electronic Number: 32
Electronic Configuration: 1s2 2s2 2p6 Electronic Configuration: 1s2 2s2
3s2 3p2 2p6 3s2 3p6 3d10 4s2 4p2
Valance electrons: 4 Valance electrons: 4

16
 Intrinsic Semiconductor

Two-dimensional representation of the Crystalline Structure

intrinsic semiconductor crystal (Diamond Cubic)

 At 0 Kelvin, all electrons are “locked” in covalent bonds → Behave like insulator
 At room temperature, thermal energy breaks some covalent bonds → creating free
electrons and “holes” → Allows conduction
• Hole: empty space left by electron
– Hole “moves” as adjacent electron move into its space
– Hole behaves like a positively charged particle 17
 Intrinsic Semiconductor
• Thermal generation results in free electrons and holes in equal numbers
and hence equal concentrations (number of charge carriers per unit
volume, cm3).
• The randomly moving free electrons fill some of the holes. This process,
called recombination, results in the disappearance of free electrons and
holes.
• In thermal equilibrium, the recombination rate is equal to the generation
rate, that means the concentration of free electrons ‘n’ is equal to the
concentration of holes ‘p’,

ni: intrinsic carrier concentration for the concentration of the free electrons, as
well as that of the holes.

• Product of the hole and free-electro concentration

18
B:material-dependent parameter for silicon = 7.3×1015cm−3K−3/2;
T: temperature in K;
Eg: bandgap energy, is 1.12 electron volt (eV) for silicon;
k: Boltzmann’s constant (8.62×10−5 eV/K).

Bandgap energy, Eg is the minimum energy required to break a

covalent bond and thus generate an electron-hole pair.

19
 Extrinsic or Doped semiconductor
• N-Type: doping pentavalent impurity (Phosphorus, P and Arsenic, As) to
the Silicon results in n type extrinsic semiconductor
• P-Type: doping trivalent impurity (Boron, B and Aluminum, Al) to the
Silicon results in p type extrinsic semiconductor

20
 N-Type Semiconductor
• Electron concentration can be greatly increased by doping pentavalent
impurity (Phosphorus, P and Arsenic, As).
• Each phosphorus atom donates a free electron to the silicon crystal, and
the Phosphorus impurity is called a donor.
• Donor impurity concentration

• @ thermal equilibrium

• Hole concentration in n-type

• nn >> ni >> pn
• Electrons → majority carrier
• Holes → minority carriers
A silicon crystal doped with a pentavalent impurity
21
 P-Type Semiconductor
• Hole concentration can be greatly increased by doping trivalent impurity
(Boron, B).
• Each Boron atom accepts an electron from a neighboring atom, thus
forming covalent bonds → Boron impurity is called a acceptor.
• Acceptor impurity concentration

• @ thermal equilibrium

• Electron concentration in p-type

• pp >> ni >> np
• Holes → majority carrier
• Electrons → minority carriers
A silicon crystal doped with a trivalent impurity22
 Currents (flow of charge particles) in semiconductors
(a) Drift: which is the movement caused by electric fields
(b) Diffusion: which is the flow caused by variations in the concentration,
that is, concentration gradients.
Electrons drift velocity
Drift Currents
Drift current density due to electron drift

Hole drift velocity

Drift current density due to hole drift

Total Drift current density

Directions of applied electric field, carrier conductivity of the semiconductor

drift velocity and drift current density

Conductivity of a semiconductor can be controlled by selective doping which

enables the fabrication of variety of electronic devices 23
 Diffusion Current
In the diffusion process, particles flow from a region of high concentration to
a region of lower concentration

A bar of silicon (a) into which holes are injected

The holes diffuse in the +ve x-direction The electron diffuse in the +ve x-
and hole diffusion current in the same direction and electron diffusion current
direction. in the opposite direction. 24
Diffusion current density due to the diffusion of electrons

Diffusion current density due to the diffusion of holes

where, e → magnitude of the electronic charge,

dn/dx → electron concentration gradient, and
Dn → electron diffusion coefficient
dp/dx → hole concentration gradient
Dp → hole diffusion coefficient

Einstein relationship: relationship between D and μ

The total current density is the sum of the drift and diffusion components
Jsemiconductor = Jdrift + Jdiffusion 25
 pn Junction
• p-type semiconductor in contact with n-type
• Basic building blocks of semiconductor devices
– Diodes,
– Bipolar junction transistors (BJT),
– Metal-oxide-semiconductor field effect transistors (MOSFET)

Cross-sectional view of pn junction diode

Symbol of pn junction diode 26

 pn Junction with open-circuit terminals

In the open-circuit case, drift and diffusion currents are same in magnitude
but opposite in direction
Net current = ID – IS = 0
27
 pn Junction with open-circuit terminals
• The holes of P-side diffuse towards N-side and electrons of N-side
diffuse towards P-side → diffusion current, ID
• At pn junction, the diffused electrons and holes recombine and create
Depletion region (immobile ions)

• Depletion width:

• The immobile ions establish an electric field, and create a potential

difference between p and n-sides.
• This potential is called built-in potential:

VT : thermal voltage (= 26 mV at room temp), NA : acceptor concentration on p-side, ND :

donor concentration on n-side, ni : intrinsic carrier concentration (=1.5×1010 cm−3 at room
temp), q: electron charge, εs : permittivity of silicon =1.04×10−12 F/cm 28
 pn Junction with open-circuit terminals
• Due to the electric field E, the thermally generated minority carriers
holes in the n material and electrons in the p material move toward the
junction and get swept across the depletion region
• Electrons moved by drift from p to n and holes moved by drift from n
to p, add together to form the drift current IS, whose direction is from
the n side to the p side of the junction
• The drift current is determined by the number of minority carriers that
make it to the edge of the depletion region; any minority carriers that
manage to get to the edge of the depletion region will be swept across
by E irrespective of the value of E or, correspondingly, of V0.
• Under open-circuit conditions no external current exists; thus the two
opposite currents across the junction must be equal in magnitude:

29
 Forward-biased pn Junction

dc voltage

Cathode
Anode

• P-side is at higher potential (more positive) with respect to n-side

• VF is externally applied forward voltage → reduces the potential barrier
voltage (V0−VF) across the depletion region → reduce depletion-region
charge → narrower depletion-region width W
30
 Forward-biased pn Junction

• Reduced the barrier voltage → increase diffusion of electrons and holes

→ increases diffusion current ID exponentially → non-linear device

• Forward current I = ID – IS
The pn junction I–V characteristic

Forward region

• pn junction can conduct a substantial current

31
 Reverse-biased pn Junction

Cathode
Anode

• n side more positive than the p side

• VR is externally applied reverse-bias voltage → increases the potential
barrier voltage to (V0+VR) → increases the depletion width → reduces
the diffusion of holes and electrons → dramatically reduces diffusion
current ID 0. 32
 Reverse-biased pn Junction
• Very small drift current almost-constant current equal to IS flows due to the
drift across the depletion region of the thermally generated minority
carriers
• current saturates → the name saturation current (function of temperature)
Net current I = ID – IS = 0 - IS

• pn junction conducts a very small and

almost-constant current equal to IS

Reverse region

VLAB forward bais experiment The pn junction I–V characteristic

http://vlabs.iitkgp.ernet.in/be/exp5/index.html# 33
Depletion Width Under Bais

34
 Capacitance in pn Junction
Depletion capacitance

Parallel Plate Capacitance:

Plate separation, W, is voltage dependent:

Variable capacitance:

Voltage variable capacitor → varactor diode 35

 Reverse Breakdown
At certain increased reverse-bias voltage V = VZ , a very large reverse current
flows. This phenomena is called junction breakdown: zener effect and avalanche
effect

Zener breakdown occurs when the electric field in the

depletion layer increases to the point of breaking
covalent bonds and generating electron–hole pairs. The
generated electrons swept by the electric field into the n
side and the holes into the p side → constitute a large
reverse current across the junction

Avalanche breakdown occurs when the minority

carriers that cross the depletion region under the
influence of the electric field gain sufficient kinetic
energy to be able to break covalent bonds in atoms with
which they collide. This process keeps repeating in the
fashion of an Avalanche → large value of reverse
current
36
 Difference between Avalanche and Zener Breakdown

Avalanche Breakdown Zener Breakdown

• Occurs in lightly doped diodes • Occurs in heavily doped diodes
• Occurs due to collision of electron • Occurs due to strong electric field
with atom (impact ionization) (tunneling effect)
• Higher breakdown voltage • Slightly less breakdown voltage
• With increase in temperature, • With increase in temperature,
breakdown voltage increases breakdown voltage decreases

Breakdown characteristics reference:

https://circuitglobe.com/wp-content/uploads/2017/05/breakdown-characteristic.jpg
Difference reference: https://youtu.be/EzlSafjMltc 37
Two-dimensional The breaking of a covalent
representation of single crystal bond for T > 0 K creating
silicon at T = 0 K; all valence an electron in the
electrons are bound to the conduction band and a
silicon atoms by covalent positively charged “empty
bonding state”

38
Since both IS and VT are functions of temperature, the forward i–v
characteristic varies with temperature,

Temperature dependence of the diode forward characteristic. At

a constant current, the voltage drop decreases by approximately
2 mV for every 1°C increase in temperature.

39
 Ideal Diode and circuit model
• Ideal diode is the most fundamental nonlinear circuit element
• RB: no current flows and the ideal diode behaves as an open circuit so it is
said to be cut off, or, simply off.
• FB: any current can flow with zero voltage drop therefore ideal diode
behaves as short circuit and it is said to be turned on, or simply on.

Diode circuit symbol

i–v characteristic
Ideal diode equivalent circuit in the
RB and FB 40
41
The Forward-Bias Region

For appreciable current i in the forward direction, specifically for I

>>IS, Eq. of i can be approximated by the exponential relationship

• cut-in voltage - current is negligibly small for v smaller than about 0.5 V
• For a “fully conducting” diode, the voltage drop lies in a narrow range,
approximately 0.6 V to 0.8 V.
• This gives rise to a simple “model” for the diode where it is assumed that
a conducting diode has approximately a 0.7 V drop across it
42
The Reverse-Bias Region

The reverse-bias region of operation is entered when the diode voltage v

is made negative and current

The Breakdown Region

The breakdown region is entered when the magnitude of the reverse

voltage exceeds a threshold value that is specific to the particular diode,
called the breakdown voltage.

43
Modeling the Diode Forward Characteristic

• Graphical Analysis Using the Exponential Model

44
• The curve represents the exponential diode equation
• The straight line represents load line
• The load line intersects the diode curve at point Q, which represents
the operating point of the circuit. Its coordinates give the values of
ID and VD.

45
 Zener Diodes

knee current

Symbol and Model for the zener diode

• The very steep i–v curve that the
diode exhibits in the breakdown
region and the almost-constant
voltage drop that this indicates
suggest that diodes operating in the
breakdown region can be used in
the design of voltage regulators.
• The voltage regulators are circuits that provide a constant dc output voltage in
the face of changes in their load current and in the system power-supply
voltage.
• In normal applications of zener diodes, current flows into the cathode, and the
cathode is positive with respect to the anode. 46
corresponding to current change ΔI the zener voltage changes by ΔV, which is
related to I by

Resistance rz is the incremental resistance of the zener diode at operating

point Q. It is also known as the dynamic resistance of the zener

A 0.5-W, 6.8-V zener diode can operate safely at currents up to a maximum of

about 70 mA.

47
• Diode rectifier forms an essential building block of the dc power
supplies required to power electronic equipment.

• The dc voltage VO is required to be as constant as possible in spite

of variations in the ac line voltage and in the current drawn by the
load.

Block diagram of a dc power supply

48
• The diode rectifier converts the input sinusoid vS to a unipolar output,
which can have the pulsating waveform
• This waveform has a nonzero average or a dc component, its
pulsating nature makes it unsuitable as a dc source for electronic
circuits, hence the need for a filter.
• The variations in the magnitude of the rectifier output are
considerably reduced by the filter block
• The output of the rectifier filter, though much more constant than
without the filter, still contains a time-dependent component, known
as ripple.
• To reduce the ripple and to stabilize the magnitude of the dc output
voltage against variations caused by changes in load current, a
voltage regulator is employed

49
• Half-wave rectifier → all voltages below zero are eliminated
• It utilizes alternate half-cycles of the input sinusoid
Input voltage

Output voltage

Half wave Rectifier equivalent circuit

Transfer characteristics 50
 Application of Diode: Rectifier
Half-wave Rectifier (considering constant voltage drop across diode)

Transfer characteristic

Input and output waveforms 51

Two important parameters must be specified:
• current-handling capability determined by the largest current the diode
is expected to conduct
• peak inverse voltage (PIV) that the diode must be able to withstand
without breakdown, determined by the largest reverse voltage that is
expected to appear across the diode. PIV = Vs

52
• Full-wave Rectifier (considering constant voltage drop across diode)
• The full-wave rectifier utilizes both halves of the input sinusoid.

PIV = 2Vs−VD
≈ twice of the half-wave rectifier

• The transformer secondary winding is center-tapped to provide two

equal voltages vS across the two halves of the secondary winding
with the polarities indicated
• For +ve half cycle, D1 conducts while for –ve half cycle D2
conducts
• current through R always flows in the same direction, and thus vO
will be unipolar
53
Input and output waveforms

Transfer characteristic 54
 Application of Diode: Rectifier
Full-wave (Bridge) Rectifier (considering constant voltage drop across diode)

Advantage of the bridge rectifier:

• Does not require a center-tapped
transformer
• PIV is about half the value for the
full-wave rectifier with a center-
tapped transformer.
PIV = Vs−2VD+VD= Vs−VD

Input and output waveforms 55

 Application of Diode: Wave shaping circuits

• Clipper (Limiter) → used to eliminate portions of a signal that are

above or below a specified level.
• It can be used to limit the input voltage to an electronic circuit so as to
prevent breakdown of the transistors in the circuit
• Example: half-wave rectifier which eliminate all voltages below zero.

General voltage transfer characteristics of a limiter circuit

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• Double limiter—works on both the positive and negative peaks of an
input waveform
• It acts as a linear circuit, providing an output proportional to the input,
vO = KvI for inputs in a certain range, L−/K ≤ vI ≤ L+/K
• If vI exceeds the upper threshold L+/K , the output voltage is limited or
clamped to the upper limiting level L+.
• If vI is reduced below the lower limiting threshold L−/K , the output
voltage vO is limited to the lower limiting level L−.

voltage transfer
characteristics Input sine wave and clipped output
(clipping off its two peaks)
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 Single diode clipper circuit

Vγ is voltage drop across diode

 The diode D1 is off as long as vI < VB + Vγ . With D1 off, the current is
approximately zero, the voltage drop across R is essentially zero, and
the output voltage follows the input voltage.
 When vI > VB + Vγ , the diode turns on, the output voltage is clipped,
and vO equals VB + Vγ .

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Double Limiter-Positive and negative clipping can be performed simultaneously
by using a double limiter or a parallel-based clipper

vO = vI as long as –(VB2 + Vγ) < vI < VB1 + Vγ

vO = VB1 + Vγ when vI > VB + Vγ.
vO = –(VB2 + Vγ) when vI < -(VB2 + Vγ)

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The battery in series with the input signal causes the input signal to be
superimposed on the VB dc voltage.

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 Application of Diode: Wave shaping circuits
• Clamper (dc restorer) → used to shift the entire signal voltage by a dc
level without changing shape of signal
• Assume that the capacitor is initially uncharged.
• During the first 90 degrees of the input waveform,
the voltage across the capacitor follows the input,
and vC = vI (assuming Vγ = 0).
• After vI and vC reach their peak values, vI begins to
decrease and the diode becomes reverse biased.
• Ideally, the capacitor cannot discharge, so the
voltage across the capacitor remains constant at vC
= VM.

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square-wave input and output signals

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Diode Circuits: Logic Gates
Two-input OR Gate

Two-input AND Gate

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 Transistor
Bipolar Junction Transistor (BJT) consists of three semiconductor regions: the
emitter region (n type), the base region ( p type), and the collector region (n
type). Such a transistor is called an npn transistor.
Another transistor, a dual of the npn has a p-type emitter, an n-type base, and a p-
type collector, and is appropriately called a pnp transistor.

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• The basic transistor principle is that the voltage between two
terminals controls the current through the third terminal.
• The two pn junctions are sufficiently close together to be called
interacting pn junctions. The operation of the transistor is therefore
totally different from that of two back-to-back diodes
• Current in the transistor is due to the flow of both electrons and
holes, hence the name bipolar.

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The transistor consists of two pn junctions, the emitter–base junction (EBJ) and
the collector–base junction (CBJ). Depending on the bias condition (forward or
reverse) of each of these junctions, different modes of operation of the BJT are
obtained

• The active mode is the one used if the transistor is to operate as an amplifier.

• Switching applications (e.g., logic circuits) utilize both the cutoff mode and
the saturation mode. As the name implies, in the cutoff mode no current
flows because both junctions are reverse biased

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 Operation of the npn Transistor in the Active Mode

• The voltage VBE causes the p-type base to be higher in potential than the n-type
emitter, thus forward biasing the emitter–base junction.
• The collector–base voltage VCB causes the n-type collector to be at a higher
potential than the p-type base, thus reverse biasing the collector–base junction.
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Current Components

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70
71
Large-signal equivalent-circuit models of the npn and pnp BJT operating in the forward
active mode

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For vCB going negative to approximately −0.4 V, the CBJ begins to
conduct sufficiently that the transistor leaves the active mode and enters
the saturation mode of operation, where iC decreases

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 Transistor Characteristics

The iC–vBE characteristic for an npn transistor

• The iE –vBE and iB–vBE characteristics are also exponential but with
different scale currents: IS/α for iE, and IS/β for iB.
• For a pnp transistor, the iC –vEB characteristic will look identical,
with vBE replaced with vEB.
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75
 Common-base npn transistor output characteristics

• When the CBJ is reverse biased, then for constant values of emitter current,
the collector current is nearly equal to iE.
• These characteristics show that the common-base device is nearly an ideal
constant-current source. 76
CB npn Transistor in saturation mode

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• This current, denoted ICBO, is the reverse current flowing from collector to base
with the emitter open-circuited (hence the subscript O).
• This current is usually in the nA range.
• As with the diode reverse current, ICBO contains a substantial leakage
component, and its value is dependent on vCB. ICBO depends strongly on
temperature, approximately doubling for every 10°C rise.

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79
The pnp Transistor

• Voltage VEB causes the p-type emitter to be higher in potential than the
n-type base, thus forward biasing the emitter–base junction.
• The collector–base junction is reverse biased by the voltage VBC,
which keeps the p-type collector lower in potential than the n-type
base. 80
Example: The transistor in the circuit of Fig. (a) has β =100 and exhibits
a vBE of 0.7 V at iC =1 mA. Design the circuit so that a current of 2 mA
flows through the collector and a voltage of +5 V appears at the
collector.

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82
83
84
Dependence of iC on the Collector Voltage -The Early Effect

• The transistor is connected in the common-emitter configuration; that

is, here the emitter serves as a common terminal between the input and
output ports.
• At each value of VBE, the corresponding iC–vCE characteristic curve can
85
be measured
• At low values of vCE (lower than about 0.3 V), as the collector voltage
goes below that of the base by more than 0.4 V, the collector–base
junction becomes forward biased and the transistor leaves the active
mode and enters the saturation mode.
• When extrapolated, the characteristic lines meet at a point on the
negative vCE axis, at vCE = -VA (typically range between 10 V to 100 V).
• VA is known as Early voltage
• At a given value of vBE, increasing vCE increases the reverse-bias
voltage on the CBJ, and thus increases depletion width region of this
junction.
• This in turn results in a decrease in the effective base width W and iC
increases proportionally.
• IS is inversely proportional to W and that iC increases proportional to IS
• This is the Early effect and also known as the base-width modulation
effect.

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• The nonzero slope of the iC–vCE straight lines indicates that the
output resistance looking into the collector is not infinite

• The finite output resistance ro can have a significant effect on the

gain of transistor amplifiers.

• The output resistance ro can be included in the circuit model of the

transistor

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Alternative Form of the Common-Emitter Characteristics

• Here the base current iB rather than the base–emitter voltage vBE is
used as a parameter.
• That is, each iC–vCE curve is measured with the base fed with a
constant current IB.

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• The iC–vCE curves in saturation are rather steep, indicating that the
saturated transistor exhibits a low collector-to-emitter resistance
RCEsat ,

• A simplified equivalent-circuit model of the saturated transistor.

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Transistor Breakdown

The maximum voltages that can be applied to a BJT are limited by the
EBJ and CBJ breakdown effects

90
Example:
For the circuit in Fig., it is required to determine the value of the voltage VBB
that results in the transistor operating
(a) in the active mode with VCE =5 V
(b) at the edge of saturation
(c) deep in saturation with βforced = 10
For simplicity, assume that VBE remains constant at 0.7 V. The transistor β is
specified to be 50.

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92
93
94
 Simplified Models for the Operation of the BJT in DC Circuits

• A quick check of the terminal voltages will indicate whether the transistor is
cut off or conducting.
• If it is conducting, we have to determine whether it is operating in the active
mode or in saturation. 95
Example:
Determine all node voltages and branch currents. Assume β is 100.

96
97
Example:

Transistor is in the cutoff mode of operation

98
Determine the voltages at all nodes and the currents through all branches.
Assume β = 100.

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 Voltage Transfer Characteristics
A plot of the voltage transfer characteristics (output voltage versus input voltage)
can also be used to visualize the operation of a circuit or the state of a transistor.

Here the output voltage vCE is given by

100
Example: Develop the voltage transfer curves for the circuits shown in Figures
Assume npn transistor parameters of VBE(on) = 0.7 V, β = 120, VCE(sat) = 0.2 V

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The transistor as an amplifier

• VBB is a dc voltage to bias the transistor at a particular Q- point and vs is the ac

signal that is to be amplified.
• To use the circuit as an amplifier, the transistor needs to be biased with a dc
voltage at a quiescent point (Q-point), as shown in the figure, such that the
transistor is biased in the forward-active region

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If a time-varying (e.g., sinusoidal) signal is superimposed on the dc input
voltage, VBB, the output voltage will change along the transfer curve producing
a time-varying output voltage

If the transistor is not biased in the active region (biased either in cutoff or
saturation), the output voltage does not change with a change in the input
voltage.

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