Topic I: Digital Logic Basics

(Boolean Algebra, Logic Gates, Number Systems, Codes, Error Detection)

1.​ The simplified SOP expression of $f(A,B,C) = \sum(m_0, m_1, m_4, m_6, m_7)$ is
________.
2.​ The given Boolean expression $(BC' + A'D)(AB' + CD')$ is equivalent to ________.
3.​ The complement of the function $F(a,b,c,d) = \pi M(1,3,4,10,12,13,14,15)$ is ________.
4.​ ________ logic function gives high output if and only if all of its inputs are zeroes.
5.​ Select the equivalent BCD representation for 83.
6.​ $(12)_{10}$ converted sequentially into its equivalent: a) binary followed by b) BCD
followed by c) Excess-3. Determine the final representation.
7.​ Identify the equivalent expression for the function $f(X_1, X_2, X_3, X_4) = X_3X_4 +
X_2'X_4 + X_1X_4$.
8.​ Identify whether the overflow is there or not after performing the 2's complement addition
for the following numbers: a) +7 + (+2) b) +7 + (-2).
9.​ Derive the simplest Sum-of-Products (SOP) and Product-of-Sums (POS) expressions for
the function $f(x_1,x_2,x_3,x_4) = x_1x_3'x_4' + x_2x_3'x_4 + x_1x_2'x_3'$.
10.​The solutions to the quadratic equation $x^2 - 11x + 22 = 0$ are $x=3$ and $x=6$. What
is the base of the numbers?
11.​NAND is more sensitive to ________.
12.​Simplify $Y = AB' + (A'+B)C$.
13.​An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)
............ gate.
14.​Binary equivalent of Gray code 1100001101011 is ________.
15.​Binary equivalent of 2421 BCD code 001110111101 is ________.
16.​Minimum NAND gates used for realizing half subtractor if realized using only two-input
NAND gates is ________.
17.​A decimal number is represented using one of the weighted codes as
1100101000111111. Identify the weighted code and write the corresponding decimal
number.
18.​The simplified form of $X+X'Y$ is ________.
19.​$(23)_{10}$ is subtracted from $(16)_{10}$ using 9's complement method. The resulting
answer is ________.
20.​A bit-by-bit multiplication is equivalent to the ________ logical operation.
21.​Binary equivalent of the gray code number 101110 is ________.
22.​Which of the following are weighted as well as self-complementary codes?
23.​Total Number of 2-input & 3-input NAND gates required to realize the function $F =
((C'.B.A)'(D'.C.A)'(C'.B'.A)')'$ is ________.
24.​Simplest realization of Ex-NOR logic using two-input NAND/NOR only requires ______
gates.
25.​Minimum number of half adders required to implement 3-input NOR gate using ONLY
half adders are ________.
 26.​Perform 6-bit binary subtraction operation on the following decimal numbers using 2’s
complement addition: i. Subtract 12 from 7 ii. Subtract 17 from 23 iii. Subtract 29 from
23.
27.​Find the 9's complement of 98127634.
28.​Convert the following numbers from a given base to the other base indicated: i.
$(356.89)_{10}$ to $(\quad)_8$ ii. $(DE.C8)_{16}$ to $(\quad)_{10}$.
29.​Reduce the following Boolean expressions to the indicated number of literals:
○​ i. $A'C' + ABC + AC'$ to three literals.
○​ ii. $A'B'C + A'B'C' + A'BC + A'BC'$ to three literals.
30.​Express the complement of the function as a sum of minterms and implement it using
basic gates: $F(A,B,C,D) = \sum m(0,2,6,7,13,14)$.
31.​Simplify the following expressions and implement them with two-level NAND gate
circuits: $AB' + ABD + ABD' + A'C'D' + A'BC'$.
32.​Reduce the following Boolean expressions to the required number of literals:
○​ i. $(CD)' + A + A + C'D + AB$ to three literals.
○​ ii. $(A+C+D)(A+C+D')(A'+C'+D)(A'+B')$ to 4 literals.
33.​Determine the binary code for each of the ten decimal digits using a weighted code with
weights 7, 4, 2 and 1.
34.​List and briefly explain the Huntington postulates for Boolean algebra.
35.​Using theorems and postulates, prove the following Boolean identities.
36.​Draw a logic diagram using only two–input NAND gates to implement the following
expression: $(AB + A'B') ( CD' + C'D )$.

37.​Simplify using K-map: $x’y’+ yz+x’yz’$.

38.​Simplify and implement with 2 level NAND gates: $ab’ + abd + abd’ + a’c’d’ + a’bc’$.
39.​Explain 3-state gate.
40.​What is “Self complementing code”? Explain a non-weighted self-complementing code.
41.​Implement a two-input NAND gate with Transistor Transistor Logic (TTL).
42.​Construct the TTL circuit for: (i) NOT gate (ii) NAND gate.
43.​Define Noise Margin. Write down the equations for low noise margin and high noise
margin.
44.​Explain the CMOS realization of a NAND gate.

45.​Construct CMOS NOR gate. Write the truth table and transistor states.
46.​Explain the following gate parameters: a) Noise margin b) Propagation delay c) Fan in.
47.​Implement a 2 input OR gate function using CMOS logic.
48.​Evaluate: A & NOT B AND C SRA 3 XOR D.
49.​Obtain Hamming code word for data word 11001001010 at sender.
50.​Given a 8-bit data word 01011011, generate the 13-bit composite word in the hamming
code that corrects single errors and detects double errors.
51.​What are Error-detection and the reflected codes? Explain each of them with an
example.
Topic II: Verilog HDL & VHDL
(Coding, Testbenches, Dataflow, Behavioral, Structural)

52.​Write a structural Verilog code for the circuit shown in FigQ1A. Use the names given in
the same figure.
53.​Write a Verilog behavioural code for a 4-bit universal shift register which performs
following tasks depending on select lines S1S0.
54.​Write a Verilog code for a 2:1 MUX using ‘assign’ statements and a testbench to
generate all possible test vectors for the above MUX and observe the corresponding
outputs.
55.​Write the truth table for 8 to 3 priority encoder. Develop the behavioural Verilog code for
the same using for loop.
56.​Write a Verilog code for one digit BCD adder using parallel adder structure.
57.​Write a structural Verilog code for 2-bit comparator using 1-bit comparator and built-in
primitives.
58.​Write sequential Verilog code for synchronous modulo-8 Gray code counter.
59.​Write a sequential Verilog code for 4-bit ripple carry adder using 1-bit full adder as basic
block.
60.​Write a dataflow Verilog code for 2-to-4 decoder with active low enable input and active
low outputs.
61.​Write the structural Verilog code for 8:1 multiplexer using 2:1 multiplexer.
62.​Write the Verilog code for 3 input NAND gate using User defined primitive (UDP).
63.​Write the sequential Verilog code for positive edge triggered J-K Flipflop.
64.​Write switch level Verilog code of 3 input NOR gate using PMOS and NMOS switches.
65.​Write sequential Verilog code for one digit BCD counter and display on seven segment
(common cathode).
66.​Write dataflow Verilog HDL code for 4-bit magnitude comparator.
67.​Write the sequential Verilog code for negative edge triggered 4-bit binary-to-gray code
converter with active high reset.
68.​Write a sequential Verilog code for 4-bit Ring counter.
69.​Write structural Verilog code for 4-bit adder/subtractor using full adder and 2-input XOR.
70.​Write structural Verilog code for Mod-8 asynchronous counter using T flip-flop.
71.​Write structural Verilog code for positive edge triggered D flip-flop.
72.​Write a behavioral Verilog code for BCD adder and display on seven segment.
73.​Write Verilog code for JK flip flop. Use it to write structural code for 3 bit UP counter.
74.​Draw state diagram and write Verilog code for sequence detector (1010 and 011).
75.​Use gate level model Verilog HDL to realize digital circuit for a night-light (lamp_lit logic).
76.​Develop Verilog HDL code for 4 bit universal shift register.
77.​Write Verilog HDL code for one bit magnitude comparator (dataflow).
78.​Draw state diagram and develop Verilog behavioral code for keypad lock FSM.
79.​Develop Verilog HDL code for 3 bit even parity generator (gate level).
80.​Write functions for addition, subtraction, multiplication, division. Use procedural
assignment for function call.
 81.​Write dataflow Verilog code for the 4 to 1 Multiplexer with Delay.
82.​Write a sequential Verilog code for 8:3 Priority encoder using case statement.
83.​Write the Verilog code for a 3 input AND gate as a user defined primitive (UDP).
84.​A staircase light is controlled by two switches... Make a truth table for this system and
implement this using behavioural Verilog code using case condition.
85.​Write structural Verilog code for full adder with two half adder modules and logical gates.
86.​Write dataflow Verilog code for the 2:4 decoder with active low enable and active high
output.
87.​Write the Verilog code for 3 input NOR gate using User defined primitive.
88.​Write a VHDL code to develop a half adder using data flow model. Build four-bit full
adder using this component.
89.​Write a VHDL code for the combinational circuit using conditional assignment.
90.​Outline purpose of: Signal attributes, function declaration, component declaration,
package declaration, Generics.
91.​What are the different wait statements available in VHDL?
92.​Write and explain VHDL code for traffic light controller in PAL22V10.
93.​How to attach a package to a VHDL module?
94.​Explain concept of test bench.
95.​List various operators in VHDL and order of precedence.
96.​Write a VHDL program to detect prime number of a 4-bit input (behavioural).
97.​Write structural VHDL code to implement Gray to Binary code converter.
98.​Translate the provided code to a when…else statement.
99.​Create parameterized entity/architecture for N input multiplexer.
100.​ Differentiate signal assignment & variable assignment.
101.​ Write a behavioral Verilog code for 2 bit comparator using if else statement.

Topic III: Simplification of Boolean Functions

(K-Maps, Tabulation Method, Quine-McCluskey, VEM)

102.​ A k-map for 4 variables has ________ number of cells.

103.​ Apply consensus theorem to simplify: $g(a,b,c,d) = a'c'd' + a'bd + bcd + acd' + b'cd'$.
104.​ Solve the given function $f(a,b,c,d) = \sum m(0,4,8,13,14,15)$ using k map to find
the simplified SOP expression. Write all prime implicants and essential prime implicants.
105.​ Identify the product term that represent essential prime implicant in the following
K-map.
106.​ Choose the simplified SOP expression for the function $y(A,B,C) = \sum m(1,4,7) +
D(2,5)$.
107.​ Simplify the function $f(x_1,...x_4)$ using Karnaugh map to obtain the minimum-cost
SOP expression assuming that there are also don’t-cares defined as $D = \sum
m(9,12,14)$.
108.​ Make use of functional decomposition to find the minimum-cost circuit for the
function $f(x_1,...x_4) = \sum m(0,4,8,13,14,15)$.
109.​ Simplify the following expression using K-map. Write all the essential prime
implicants and find the minimum cost SOP expression: $F(a,b,c,d) = \sum
m(1,3,4,5,7,8,9,11,12,15)$.
110.​ In a 4-variable K-map, a grouping of cells with _____ minterms eliminates the
complement of the least significant variable from the resulting term.
111.​ Identify the minimum cost SOP expression for the following function using K Map:
$F(A,B,C,D) = \sum m(0,1,4,6,7,8,10,14,15)$.
112.​ What is the cost of the obtained expression? Identify the number of prime implicants
and essential prime implicants and list them.
113.​ Simplify function ‘F’ using tabulation method.
114.​ Simplify Boolean function using Quine McCluskey method.
115.​ Simplify function ‘F’ using K-Map into product of sums form.
116.​ For the given Boolean function, determine a minimal sum using VEM technique:
$f(A,B,x,y,z)=Ax'z'+A'y'z+Ax'z+A'x'y'z+B'yz'+A'yz+B'x'z'$.
117.​ Find the POS implementation for the following and compare the cost with the SOP
form.
118.​ Obtain the minimum cost SOP and POS for the following function F using K-map:
$F(a,b,c,d,e) = \pi M(0,2,6,10,13,14,18,25,26,30)$.
119.​ Use functional decomposition to find the best implementation of the function:
$f(a,b,c,d,e) = \sum m(1,2,5,7,9,10,13,15,18,19,25,26,29,31)$.
120.​ What are the universal gates? Simplify the following Boolean expression using
Karnaugh map and draw the logic circuit using only NAND gates: $F(A,B,C,D) = \sum
m(6,7,8,9,10,12) + d(2,5,13)$.
121.​ Simplify the function F using tabulation method. Implement the simplified expression
using NAND gates only: $F(A,B,C,D,E) = \sum(0,2,7,8,9,12,15,22,28,32) + \sum
d(5,10,25)$.
122.​ Simplify the given function 'F' using tabulation method. Implement the simplified
expression using basic logic gates: $F(A,B,C,D,E) = \sum m(2,1,13,14,15,24,27,29,30) +
\sum d(0,12,16,18,25,28,31)$.
123.​ Simplify the given function ‘F’ using K- Map into product of sums form: $F(A,B,C,D,E)
= \sum m(1,3,5,7,9,11,13,15,25,27) + \sum d(2,8,21,23,28)$.
124.​ Simplify the Boolean function $F(A,B,C,D) = \pi M(0,1,6,7,9,14,15) \cdot \pi d(5,13)$
using Quine McCluskey method and draw the logic circuit using NOR gates ONLY.
125.​ Simplify the given function 'F' using tabulation method. Implement the simplified
expression using NOR gates only: $F(v,w,x,y,z) = \sum
m(1,5,9,11,13,20,21,26,27,28,29,30,31) + d(3,17,19)$.
126.​ Using Karnaugh map, determine simplified sum of products and product of sums
expressions for the function: $F(A,B,C,D,E) = \pi
M(1,3,4,5,11,14,15,16,17,19,20,24,26,28,30)$.
127.​ Simplify $F(A,B,C,D,E) = \sum(0,2,8,9,10,13,16,18,24,25,26,29,31)$ Using
Karnaugh map method.
 128.​ Simplify the following expression using the tabulation method: $F(u,v,w,x,y) = vw'x'y
+ u'v'y + uv'w'x'y + v'y' + uvx'y' + v'w'x'y$.
129.​ Minimize the following using K maps and give the minimal expressions. i. POS
expression given by $f(A,B,C,D) = \sum m(0,1,2,3,5,9,14,15) + \sum d(4,8,11,12)$. ii.
SOP expression given by $f(A,B,C,D) = \pi M(0,1,2,5,8,9,10)$.
130.​ Using tabulation method, determine the set of all prime implicants for the function
and hence obtain the minimal form of given function: $F(W,X,Y,Z) =
\sum(0,1,2,7,8,9,10,15) + d(3,12)$.
131.​ Simplify the Boolean function $F(A, B, C, D, E) = \sum(6, 9, 13, 18, 19, 25, 27, 29,
41, 45, 57, 61)$ using TABULATION method.
132.​ Design a simplified expression in SUM of PRODUCTS for the following Boolean
functions: i) $F(A, B, C, D) = \sum(7, 13, 14, 15)$. ii) $F = x'y'z + x'yz' + xyz' + xyz$.
133.​ Solve the SoP function minimization of 5 variable K-Map using the following
expression: $F(A, B, C, D, E) = \sum(0, 2, 4, 6, 9, 11, 13, 15, 17, 21, 25, 27, 29, 31)$.
134.​ Solve the POS function minimization of 5 variable K-Map using the following
expression: $\pi M(0,2,4,7,8,10,12,16,18,20,23,24,25,26,27,28)$.

Topic IV: Combinational Logic Circuits

(Adders, MUX/DEMUX, Encoders/Decoders, Comparators, Code Converters)

135.​ How many NOT gates are required for the construction of a 4-to-1 multiplexer?

136.​ A 5:32 decoder circuit can be implemented with ________.

137.​ How many 3 to 8 decoders are required to construct a 4 to 16 decoders?
138.​ ________ has $2^n$ input lines and $n$ output lines.
139.​ ________ converts binary coded information to unique outputs such as decimal,
octal digits, etc.
140.​ Write the truth table for 8 to 3 priority encoder and design the same using basic
gates.
141.​ Design the given function $f(A,B,C)=m(0,1,4,6,7)$ using 4:1 Multiplexer.
142.​ Select the minimum number of 2:1 multiplexers required to generate a 2 input XNOR
gate without using any external gates.
143.​ Identify the number of 3-to-8 decoders and AND gates required to design an 8:1
multiplexer.
144.​ Suppose a single bit comparator compares two numbers P and Q and produce
output Z1=1 when P=Q, Z2=1 when P>Q and Z3=1 when P< Q, then select the correct
expression for Z1, Z2 and Z3.
145.​ With examples show the two cases where correction has to be made during the
addition of two BCD digits. Also show the result after correction. Using four bit binary
adders, design the single digit BCD adder.
146.​ Design a logic diagram that converts single digit BCD into its equivalent gray code.
 147.​ Design a full adder using basic logic gates starting from the truth table.

​
​

148.​ Design and implement the function using 8:1 MUX and other necessary gates.
149.​ Design the logic for BCD addition adjustment. Draw the circuit diagram for a two-digit
BCD adder using parallel adder.
150.​ Design a 4-bit Gray-to-Binary code converter and implement the same using logic
gates.
151.​ Alarm system logic design (4 sensors, alarm if 2+ are 1).
152.​ Implement $F(A,B,C) = \sum m(1,3,5,6)$ using (i) 4X1 multiplexer (ii) 2 x 1
multiplexer and a logic gate.
153.​ From the given gate level circuit, derive the Boolean expressions.
154.​ Number of 2 X 1 multiplexers required to design $2^n$ X 1 multiplexer.
155.​ Which of the following are building blocks of encoders?
156.​ Design a two-bit comparator using logic gates and draw the logic diagram.
157.​ For the function $f(w1,w2,w3) = w1w2+w1w3+w2w3$, use Shannon’s expansion to
derive an implementation using a 2-to-1 multiplexer.
158.​ Write the truth table for full adder and implement it using 2:1 multiplexers and other
necessary gates.
159.​ A 2:4 priority encoder is designed... Which variable has the highest priority?
160.​ Design a combinational circuit using half adder that adds one to a 4-bit binary
number.
161.​ Equation for valid bit 'V' for 8 to 3 priority encoder.
162.​ In a 1-bit magnitude comparator with cascading inputs, if cascading input L is 1...
163.​ The output f of a 4:1 MUX, as shown in the figure is given by...
164.​ Design a combinational circuit using minimum number of 7485 ICs, 7483 ICs. (If
A>=B, F=A+B, Else F=A+1).
165.​ Design a 2-to-4-line decoder using ONLY 2:1 Multiplexers.
166.​ Design soil moisture detecting circuit using only NOR gates.
167.​ Implement 3 input NOR gate using half adders only.
168.​ Design code converter (Excess-3 to 8 4 2 1) using basic logic gates.
169.​ If A, B and C are the inputs of a full adder, then the carry is given by...
170.​ In the given 4-to-1 multiplexer, if C1 = 0 and C0 = 1 then the output M is...
171.​ Implement the following Boolean function using 4-to-1 multiplexer and external
gates: $F(A,B,C,D) = \sum m(1,3,4,13,12,13,14,15)$.
172.​ Find the minimum number of two input NOR gates required to realize the simplified
expression of F.
173.​ The simplified expression for the most significant output Y1 of 4:2 priority encoder
is...
174.​ If the function $F(A,B,C) = \sum(0,3,4,6,7)$ is implemented using only 74153 IC, how
many 74153 ICs are used?
175.​ Outputs of cascaded 1-bit magnitude comparators.
176.​ A Full Adder can be designed using ______ half adders only.
177.​ Use a 4-to-1 multiplexer to realize the function $f(a,b,c,d) = \sum m(2,3,5,7,8,9,12)$.
178.​ (i) Design a 4-bit barrel shifter that performs the following operation using multiplexer.
(ii) Design a logic circuit that performs the following operation using multiplexer.
179.​ Design a circuit to implement 4 input EXOR gate using 4:1 multiplexers and residual
gates.
180.​ Create a collision detection circuit for a network router (3 inputs tx1, tx2, tx3; output
col). Implement using decoder and additional gates.
181.​ Design an 8-bit adder/ subtractor circuit using 74LS283.
182.​ A combinational network with 4 inputs A, B, C, and D... Implement Y using 2:1
multiplexer/s and residual gates.
183.​ Realize the output using 3:8 decoder and necessary logic gate.
184.​ Design a comparator circuit using 4 bit adder IC (74283 IC) and residual gates that
compares two 4-bit unsigned numbers.
185.​ Design a circuit using K-map which converts 4-bit XS-3 code to its equivalent BCD
code. Implement the minimum expression using NOR logic only.
186.​ Design code converter (decimal in 8 4 -2 -1 to decimal in gray) using NOR gates
ONLY.
187.​ Construct 4:2 priority encoder using basic logic gates.
188.​ Design code converter (decimal in 8 4 -2 -1 to Excess-3) using NAND gates ONLY.
189.​ Design 4-bit magnitude comparator using 7483 IC and external NOR gates.
190.​ Design full adder using 74138 IC.
191.​ Design code converter (Decimal in Gray to Excess 3) using basic gates.
192.​ Design 8:1 MUX using 2:1 MUXs only.
193.​ Design circuit for F=XY (M=0) and F=X+Y (M=1) using 74153 ICs.
194.​ Design code converter (Decimal in 8 4 -2 -1 to Gray) using 74138 ICs.
195.​ Design the following combinational circuit using minimum number of 7483 ICs and
half adder blocks. (If A<B, F=2A+4B Else F=4A+2B).
196.​ Design a 2-bit magnitude comparator using 74151 ICs.
197.​ Design code converter (Gray to self-complementary 4221) using 3 to 8 decoders.
198.​ Design BCD addition adjustment logic.
199.​ Design 2-bit comparator using logic gates.
200.​ Design 4-bit Gray-to-Binary code converter.
201.​ Implement $F(A,B,C) = \sum(1,3,5,6)$ using 4x1 and 2x1 MUX.
202.​ Design 4 to 16 line decoder using 2 to 4 line decoders.
203.​ Design 1-bit magnitude comparator with cascading inputs. Draw circuit for 4-bit.
204.​ Implement $f(A,B,C,D) = \sum(0,3,5,9)$ using optimised number 2 to 4 decoders and
additional gate.
205.​ Implement a full adder using two half-adder circuits and one OR gate.
206.​ Design a combinational circuit for conversion of code 2 4 2 1 to 8 4 2 1 code.
207.​ Use Shannon’s Expansion to implement $f(a,b,c,d,e)=bd’+cd+a’c$ taking a,b,c as
select lines. Use 8:1 multiplexer and other necessary gates.
208.​ Write the truth table for a 4 input XOR function. Implement it using least possible
number of 4:1, 2:1 multiplexers and NOT gates.
209.​ Write the truth table for full adder and implement it using i) Only 2:1 multiplexers and
NOT gates ii) 2:4 decoders and other necessary gates.
210.​ Use Shannon’s expansion to implement $f(c,b,a) = \pi M(0,4,5,6)$ using only 2:1
multiplexers.
211.​ Implement Half-adder and Full-adder block using appropriate decoders with
active-High outputs and basic gates.
212.​ Design a code converter circuit to convert 3-bit Gray code to Binary code.
213.​ Implement a BCD to XS-3 code conversion circuit using PROM.
214.​ Design a 4:2 priority encoder.
215.​ Design a combinational circuit to evaluate the arithmetic expression $D=X^2 - Y^2$
using 7483IC and external gates.
216.​ Design 5:32 decoder using 3 to 8 decoders only.
217.​ Design a single digit BCD adder using 7483 ICs and with 2:1 multiplexers.
218.​ Design an 8 to 3 line priority encoder to detect highest priority to the input with lowest
index.
219.​ Design a 2-bit magnitude comparator using ONLY two 4:1 multiplexers and minimum
external gates.
220.​ Construct a 4 to 16 line decoder using 2 to 4 line decoders only.
221.​ Design a code converter to convert a decimal digit represented in 8 4 –2 –1 code to
decimal digit represented in gray code, using only universal gates.
222.​ Design a 4-bit combinational shifter.
223.​ Using PROM of smallest appropriate size, draw the logic diagram in PLD notation to
realize the arithmetic expression F(X) = 3X +2.
224.​ Design a code converter to convert a decimal digit represented in 8 4 -2 -1 to a
decimal digit represented in gray code using NOR gates ONLY.
225.​ Construct 4:2 priority encoder using basic logic gates.
226.​ Design a logic circuit to perform arithmetic operation F=X-Y when M=0 and perform
F=X+Y when M=1 using minimum 74153ICs ONLY.
227.​ Design 1-bit magnitude comparator with cascading inputs using logic gates. Using
the same, draw the circuit to compare two 4-bit binary numbers.
228.​ Design a code converter to convert a decimal digit represented in Excess - 3 code to
a decimal digit represented in 8 4 -2 -1 code using NAND gates only.
229.​ Design a 4-bit magnitude comparator using 7483 IC and external NOR gates only.
230.​ Design a full adder using 74138 IC and minimum external gates.
231.​ Design a 2-bit x 2-bit binary multiplier using 74151 ICs and external gates.
232.​ Design a code converter to convert a decimal digit represented in 8 4 -2 -1 to a
decimal digit represented in Gray code using 74138 ICs and minimum external gates.
233.​ Design a single digit BCD adder/subtractor in which the inputs are in excess-3 code,
using 7483 ICs and logic gates.
234.​ Design a 3-bit binary to gray code converter using minimum number of 74153 ICs
ONLY.
235.​ Design a combinational circuit using 74138 IC that takes (7 5 3 -6) code as 4-bit
input and generates an output high if the input is in the range 0 to 3.
236.​ If X=0, F=Y+1 otherwise F=Y-1... design logic circuit using i) ONLY single 7483 IC ii)
Minimum number of Half adders and one external gate only.
237.​ Design Full Adder using active low output 2 to 4 decoders with enable and external
gates.
238.​ Design a 1-bit magnitude comparator using basic gates.
239.​ Design a code converter using basic gates only to convert an 8 4 -2 -1 code to
decimal digit represented in 8 4 2 1.
240.​ Devise a full adder/subtractor circuit employing a 74153 IC along with minimum XOR
gates.
241.​ Design a full adder combinational circuit using decoder.
242.​ Design a multiplexer with a 16-to-1 configuration by using 2-to-1 multiplexers only.
243.​ Design a code converter to convert a decimal digit represented in Gray code to a
decimal digit represented in excess 3 code using only basic gates.
244.​ Design 8:1 MUX using 2:1 MUXs only.
245.​ Design a 3-bit magnitude comparator using 7483 IC and NOR gates ONLY.
246.​ Design a code converter to convert a decimal digit represented in excess -3 code to
a decimal digit represented in gray code, using 74138 ICs and external gates.
247.​ Design full adder/ subtractor using minimum 4:1 Multiplexers and ONLY XOR gates.
248.​ Make use of functional decomposition to find the minimum-cost circuit for the
function f.
249.​ Design a minimal circuit for Y using only one decoder, one 2:1 multiplexer, and OR
gates.
250.​ Design a combinational unit that can act as adder and subtractor for two 4-bit
numbers.
251.​ Design a combinational circuit to convert 4-bit Binary to Gray code.
252.​ Design the specified Boolean function using 8:1 multiplexer.
253.​ Implement 4 to 16 decoder using 2 to 4 decoder using optimized number of
decoders.
254.​ Design a 2-bit magnitude comparator using basic logic gates.
255.​ Implement 4 bit BCD to excess-3 code converter circuit using basic gates.
256.​ Implement a 2-bit equality detector using a 4:1 multiplexer and additional gates.
257.​ Implement 4 to 16 decoder using 3 to 8 decoders with active low enable input signal.
258.​ Design a logic circuit to evaluate the arithmetic expression $(A^2 – B^2)$ using 7483
IC and external gates.
259.​ Design a code converter to convert a decimal digit represented in gray code to
decimal digit represented in 8 4 -2 -1 code, using 74138 ICs and external gates.
260.​ Design 2-bit magnitude comparator with cascading inputs. Using the same, design a
4-bit magnitude comparator.
261.​ Design a code converter to convert a decimal digit represented in 8 4 -2 -1 to
decimal digit represented in excess -3 code, using NAND gates only.
262.​ Using 74153 IC and external NAND gates, design a full adder.
263.​ Design a 4-bit magnitude comparator using 7483 IC and NOR gates only.
264.​ Design a 4-to-2 priority encoder using NOR gates only.
265.​ Design the combinational circuit to evaluate the algebraic expression,
$F=(X+Y)(X-Y)$ using full adders and external NAND gates.
266.​ Design a 4:2 priority encoder using basic logic gates.
267.​ Design a code converter to convert a decimal digit represented in 5 2 1 1
(self-complementing) to a decimal digit represented in excess-3 code, using 74138 ICs
and external gates.
268.​ Design a code converter to convert a decimal digit represented in gray code to a
decimal digit represented in self-complementary 4221 code using minimum number of 3
to 8 decoders.
269.​ Design the following combinational circuit using single 7485IC, 7483IC and minimum
number of full adder blocks.
270.​ Design a code converter to convert a decimal digit represented in 5 4 2 1 code to a
decimal digit represented in self-complementary 8 4 -2 -1 code using minimum number
of 3 to 8 decoders.
271.​ Design the following combinational circuit using minimum number of 7483ICs and
half adder blocks.
272.​ Design a code converter to convert a decimal digit represented in excess-3 code to a
decimal digit represented in self-complementary 5 2 1 1 code using minimum number of
3 to 8 decoders.
273.​ The below circuit accepts BCD inputs for digits 0 to 9; the output is to be 1 only if
input is odd. Design minimal logic circuit to accomplish this.
274.​ Design a combinational circuit that accepts a 3 bit number and generates an output
binary number equal to the square of the input number.
275.​ Construct a 16 x 1 MUX with two 8 x 1 MUXs and one 2 x 1 MUX. Use block
diagrams.
276.​ Design a 4-line to 2-line priority encoder include an output E to indicate that at least
one input is 1.
277.​ What are decoders? Construct a 5 x 32 decoder with four 3 x 8
decoder/demultiplexers and a 2 x 4 line decoder.
278.​ Draw Quadruple 2 to 1 line multiplexer.
279.​ Design 4 bit combinational circuit which gives 2’s complement of given input using
only XOR gates.
280.​ Design a code converter to convert a decimal digit represented in excess 3 to 8 4 -2
-1 code using 3:8 decoders and minimum external gates.
281.​ Design a code converter to convert a decimal digit represented in gray code to a
decimal digit represented in excess-3 code using 3:8 decoders and minimum external
gates.
282.​ Design a combinational circuit to perform F= A-B when control input Y=0 and
perform F= 1+2A-B when control input Y=1 using 4-bit parallel binary adders and
minimum universal gates.
283.​ Design a combinational circuit that compares two, 4-bit numbers to check if they are
equal using logic gates.
284.​ Design a 4 x 16 decoder using only 3 x 8 decoders.
 285.​ Design a 4-bit combinational shifter to function according to the Table Q.5C (00
Parallel load, 01 Rotate left once, 10 Rotate left twice, 11 Rotate left thrice).

Topic V: Sequential Logic Circuits

(Flip-Flops, Counters, Registers, FSMs)

286.​ A master slave flip-flop has the characteristics that...

287.​ The logic circuit represents... (Fig of TFF)

288.​ Refer to logic circuit shown in figure. The inputs P1P2 for the logic circuit are first
made 01 and then after a few seconds, made 11, the corresponding outputs Q1Q2 are...
289.​ Consider the following Master-Slave flip flop with the initial state on P = 0, and Q = 1.
After the first three clock cycles the output state P, Q will be...
290.​ The characteristic equation of the XY flip flop is X Q' + YQ. The output of the circuit
for X =1 and Y=1 is...
291.​ Latch is a device with...
292.​ What is the difference between ripple counter and synchronous counter?
293.​ Design an AB flip flop whose function table is given below, using a NOR latch and
external gates.
294.​ Design a 4-bit asynchronous UP counter using positive edge triggered SR flip flops.
295.​ Which of the following is FALSE with respect to Flip flops?
296.​ A ............ Counter can be implemented using three flip-flops.
297.​ Design a synchronous BCD counter that counts from 0 to 9 using D flip-flops.
298.​ A sequential circuit has two SR flip-flops A and B... Draw the state diagram and state
table.
299.​ Design a 3-bit register in such a way that it operates according to the following
function table.
300.​ Design an asynchronous ripple counter to count from 0 to 15 using negative edge
triggered D flip flop.
301.​ The circuit has JK flip flops with active low asynchronous reset inputs. Which of the
following correctly defines the function of this circuit?
302.​ An initially cleared JK flip flop is used with input J = 1 and K = Q. What will be the
reading on output Q for next 6 clock pulses?
303.​ An input sequence 101011011001 is applied to the state machine with S0 being the
initial state.
304.​ In which of the following circuit the flipflop’s output transition serves as an input
source to trigger other flipflops?
305.​ An A-B flipflop is constructed using D flipflop and is shown here in the figure. Which
of the following option correctly defines the function of A-B flipflop?
306.​ Which of the following statement is incorrect with respect to asynchronous counters?
307.​ A bit sequence of length 15 requires ______ flip flops in a sequence generator.
 308.​ Which of the following statement correctly defines Master-Slave Flipflop
characteristic?
309.​ The present output Qn = 0 and the next output Qn+1 = 1. Which of the following
inputs correctly defines this situation from the excitation table of edge triggered JK
flipflop?
310.​ Using sequential design approach, design a three-bit binary counter with D flip flop.
311.​ A register A is to implement the following register transfers... Design a single register
cell.
312.​ Explain the working principle of D Latch using four NAND gates.
313.​ Consider a synchronous sequential circuit with one input x, two D flip-flops and one
output z.
314.​ Design a ripple decade down counter using positive edge triggered T flip-flops.
315.​ Write Next state table, Excitation table and derive characteristic equation for a
flip-flop with 2 inputs L & M and one output N.
316.​ Design divide by 10 counter using IC 74LS93.
317.​ Design an asynchronous mod 16 counter using T flipflops.
318.​ Convert JK flip-flop to T Flipflop and design the circuit for the same.
319.​ Design a Single circulating one logic, in a 4-bit counter a) using IC74LS194 b) using
D flipflops.
320.​ Design synchronous sequence generator circuit that generates the sequence 0-1-2-
4-9-3-7-0 using DFF.
321.​ Design and test a circuit that checks for the sequence 010 continuously in a data
sequence using D Flip-Flop (Moore machine).
322.​ An XY Flipflop is constructed from JK Flipflop. a) Write an expression for X and Y b)
Derive the excitation table and characteristic equation for XY Flipflop.
323.​ Write the state table representation of the FSM with the Flip-Flop input equations
T1=Q2x ; T2=x ; Z=Q1Q2.
324.​ Design and implement a 4-bit shift register which performs operations as given in
Table 1B.
325.​ Implement 1010 overlapping sequence detector using Moore model.
326.​ Design a synchronous counter which goes through 0, 3,6,7 using positive edge
triggered XY flip flop.
327.​ Analyze the sequential circuit shown in Fig. 4B and draw its state diagram.

328.​ For the following state diagram, derive the expressions required for the synchronous
sequential circuit design using T flip-flops.
329.​ Explain in detail the design of a basic RS latch using NOR gates.
330.​ Explain how the restriction on the pulse width in the case of JK flip-flop can be solved
by using master/slave JK flip-flop.
331.​ Design the synchronous counter with the following repeated binary sequence: 0, 1,
2, 3, 4, 5, 6. Use JK flip‐flops.
 332.​ Analyze the following state table and perform the state reduction. Develop the state
diagram.
333.​ Develop a state diagram for the FSM that meets the following specification... (Detect
2nd occurrence of w=1).
334.​ Construct a Johnson counter which generates 8 timing signals.
335.​ Build the D-type positive edge-triggered Flip-flop using NAND gates.
336.​ Construct a 5-bit ring counter using D flip-flops.
337.​ A MN Flip Flop (FF) has 2 inputs M and N... Derive the characteristic equation...
Design Mod 8 binary down counter.
338.​ Design a counter with the repeated binary sequence 1, 3, 5, 7, 2, 4, 8, 10, 12, 14
using SR Flip Flops.
339.​ Derive the state diagram for an FSM that has an input w and an output z... (1001 or
1111 detection).
340.​ Draw the state diagram and ASM chart for a control circuit that swaps the contents of
registers R1 and R2.
341.​ A sequential circuit has three T flip-flops, A, B and C and one input x... Derive the
state table.
342.​ Draw the 3-bit Johnson counter. Write the count sequence and decoding logic.
343.​ Derive the Flip Flop (FF) input equations for a synchronous BCD down counter using
JK FFs.
344.​ Derive the sequential circuit output and Flip Flop input equations that realize the
FSM... using SR Flip-Flops.
345.​ Distinguish between the following: i) Synchronous and asynchronous clear.
346.​ Derive the characteristic equation of P-Q flipflop... Convert P-Q flipflop to D flipflop.
347.​ Design a Mealy overlapping sequence detector that detects sequence 101 using D
flipflop.
348.​ Implement 1111 overlapping sequence detector using Mealy model.
349.​ Construct a 2-bit synchronous up counter using T-flip flop.
350.​ Draw a state graph and state table to implement a sequence detector for detecting a
sequence “1101” (overlapping method) using mealy machine.
351.​ Explain testing of sequential logic using scan path testing.
352.​ Design a T flip flop from SR flip flop.
353.​ Design a synchronous sequential circuit... output V is HIGH whenever the sequence
"010011" is detected.
354.​ Using 7490 ICs ONLY, design a logic circuit which divides the frequency of the input
square wave by a factor of '100'.
355.​ What is a race around condition? How is it overcome using Master-Slave
configuration?
356.​ Design a self-starting synchronous counter using T flip flops and external gates to
count the sequence 1 -> 2 -> 4 -> 9 -> 12 -> 5 -> 1.
357.​ Give excitation table and characteristic equation for JK–flip flop.

​
358.​ Design a sequence detector circuit to detect the sequence 10101 using D–flip flops.
359.​ Using only 7490 ICs, design a counter to count between the limits 00 to 47
continuously.
360.​ Draw a 2 – bit asynchronous pre-settable UP counter logic circuit using T–flip flops.
361.​ Explain a 4 – bit ring counter with necessary logic diagram.
362.​ Construct a ring counter (sequence 1000 – 0100 -0010 -0001) using structural
modeling.
363.​ Design a sequential circuit to generate the sequence 1011 using ring counter and
external gates.
364.​ Design JK flip flop using NOR latch and external gates.
365.​ Design an asynchronous presettable counter to count from 3(16) to B(16) using D flip
flops.
366.​ Using 7490 ICs ONLY, design a counter to count from 00 to 87 continuously.
367.​ Design a sequential logic circuit to count in decimal from N2 to N1 where N2 >N1
using 7483 ICs, 74193 ICs, 74157 ICs.
368.​ Design a Moore sequence detector circuit to detect the sequence 110 and 01101
using T– flip flops.
369.​ Draw the sequential circuit for MOD – 6 Johnson counter.
370.​ An asynchronous circuit divides an input square wave by a factor of 14... Give the
circuit realization using negative edge triggered JK flip flops.
371.​ Using Mealy model, write the state diagram for detecting the binary sequence 1101.
372.​ Design SR flip flop using NAND latch and external gates.
373.​ Design a 2-digit decimal down counter using 74193 ICs.
374.​ Design a synchronous counter to count the sequence 0 → 1 → 4 → 6 → 0... Use T –
flip flops.
375.​ Draw the logic circuit of 2-bit presettable asynchronous counter using D flip flops.
376.​ Design a 4-bit synchronous up counter, using D flipflops
(0->9->2->8->3->7->4->6->5->0).
377.​ Construct a two-digit hexadecimal counter from 77H to 38H using 74193 ICs.
378.​ Design a asynchronous sequential circuit using JK flipflops and external gates to
generate the sequence 10110.
379.​ Design a 3-bit asynchronous down counter using T Flip Flops.
380.​ Illustrate how SR flip flop can be converted to JK flip flop.
381.​ Design a sequence detector to detect 1010 with overlapping using Moore model with
positive edge triggered D flip flop.
382.​ Design MOD 14 asynchronous counter using i. 7493 ICs ii. 7490 ICs.
383.​ Design a 2 – bit synchronous UP/Down counter using negative edge triggered T –
flip flops.
384.​ Using 74193 ICs, 7485 ICs and external gates, design a 2 – digit decimal DOWN
counter.
385.​ Design a sequence generator circuit to generate the sequence 1101000 using
asynchronous down counter.
386.​ Design a sequence detector circuit... output Z is HIGH whenever the sequence
“1001” is detected.
387.​ Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and inverter only.
388.​ Design the circuit diagram for a sequence detector to detect a sequence 011 using
Mealy model.
389.​ Design an Asynchronous UP counter to count from 2 to 6 continuously using positive
edge triggered JK - flip flops.
390.​ Design a Synchronous counter to generate asequence: 0, 3, 5, 6, 0.
391.​ Draw the circuit diagram of a 2-bit Up-Down Asynchronous counter using pos-edge
D flip flops.
392.​ Devise a counter circuit employing D flip-flops... to generate the recurrent binary
sequence 0, 1, 2, 4, 6...
393.​ Convert the Jk flip flop to D Flip flop.
394.​ Design a sequence detector to detect three or more consecutive 1's in a sequence of
bits using Mealy model.
395.​ Design an Asynchronous DOWN counter to count from 6 to 2 continuously using
negative edge triggered T-flip flops.
396.​ Design a sequence generator using synchronous counter with states 0→3→2→1→0
that generates the sequence '1100'.
397.​ Design a Synchronous DOWN counter that follows a 3 - bit Gray code sequence.
398.​ Design a 4-bit sequential up counter using JK flipflop to count the sequences from 3
to 9.
399.​ Design a sequence detector circuit to detect the sequence 1101...
400.​ Construct a T flip-flop using basic NOR latches.
401.​ Using only JK - flip flops, design a MOD 10 counter circuit.
402.​ Design a sequence detector circuit... output Z is HIGH whenever the sequence "101"
is detected... Implement using T - flip flops.
403.​ Design JK - flip flop using NAND latch and external gates.
404.​ Design a 4 - bit asynchronous presettable Down counter to count from (1100)2 to
(0110)2 using negative edge triggered D - flip flops.
405.​ Using 74193 ICs, 7485 ICs and external gates, design a 2 - digit decimal UP counter.
406.​ Design a sequence generator circuit to generate the sequence 10111001 using
Johnson counter.
407.​ Using ONLY 7490 ICs, design a MOD 10 counter circuit to generate an output
waveform with 50% duty cycle.
408.​ For the following state diagram, derive the expressions required for the synchronous
sequential circuit design using JK flip-flops.
409.​ Demonstrate SR latch (basic Flip Flop circuit) using NAND gates with its function
table.
410.​ It is required to develop a system to swap the contents of two n-bit registers.
411.​ Construct JK Flip Flop from D Flip Flop.
412.​ Design the synchronous counter with the following repeated binary sequence: 0, 1,
2, 4, 6. Use D flip‐flops.
413.​ Analyze the following state diagram and perform the state reduction.
414.​ Distinguish between Moore and Mealy models of sequential circuit design.
415.​ Design 3-bit Johnson counter.
416.​ Draw the state table and design the synchronous sequential circuit for the following
state diagram using JK FF.
417.​ Design a 4-bit ring counter using D flip-flops.
418.​ Design a mod-6 ripple up counter using negative edge triggered T Flipflops.
419.​ Design a synchronous 3-bit Gray code counter using positive edge triggered T
flipflops.
420.​ Design sequence detector to detect the overlapping sequence 0101 using Mealy
model with positive edge triggered D Flipflop.
421.​ Convert D flipflop to JK flipflop. Write characteristic equations of JK flip flop.
422.​ Design an asynchronous up-counter using positive edge-triggered JK flip-flops to
divide the input frequency by 8.
423.​ Design a self-starting counter using positive edge triggered D flip-flop to generate the
sequence 1, 2, 5, 7 and repeat.
424.​ Design a sequential circuit using Mealy machine that can detect the overlapping
sequence 1001 using negative edge triggered D flipflops.
425.​ Convert D flip-flop to JK flip-flop.
426.​ Design asynchronous UP/DOWN counter using negative edge triggered JK – flip
flops to generate a square waveform (50 % duty cycle) of frequency 1/8 of input clock
waveform.
427.​ Design a JK – flip flop using D – flip flop and external gates.
428.​ Design a synchronous UP/DOWN counter using JK – flip flops and external gates to
count the sequence 1→3→5→7→2→1.
429.​ Using 7490 IC and minimum external gates, design a sequential circuit to generate
the sequence 00111011.
430.​ Design a MOD – 10 twisted ring counter using JK – flip flops.
431.​ Using 74193 ICs and external gates, design a 2 – digit hexadecimal down counter
which counts from 87H to 19H and repeats.
432.​ Design a sequence detector... output Z is HIGH whenever the sequence “11011” is
detected... Implement using T– flip flops.
433.​ Design MOD–8 ring counter using JK – flip flops.
434.​ Design a synchronous 3- bit gray code UP/DOWN counter using JK – flip flops.
435.​ Derive the characteristic equation of SR flipflop.
436.​ Design a sequence detector... output Z is HIGH whenever the sequence “00010” is
detected... Implement using D - flip flops.
437.​ Show that, each state of a MOD-6 Johnson counter can be decoded using a two
input AND gate.
438.​ Design SR – flip flop using NOR Latch.
439.​ Design a self-correcting synchronous counter using T – flip flops and minimum
number of external gates to count the sequence...
440.​ What is race around condition? How is it overcome in T – flip flop using Master-Slave
configuration?
441.​ Design SR – flip flop using D – flip flop and external gates.
442.​ Design a sequence detector with one input Y and one output Z using Moore model...
sequence “1101!”... using JK– flip flops.
443.​ Design a 3 – bit universal shift register using D – flip flops and Multiplexers.
444.​ Using 7493 ICs, 7485ICs and external gates, design a 2 – digit decimal counter
which counts from 00 to N (00 < N < 99) and repeats.
445.​ Construct a hexadecimal up counter to count from 0 to 41H using only one 7490 IC
and one 7493 IC.
446.​ Design the AB flip flop using D flip flop and external gates.
447.​ Design a JK flip flop using a basic NOR latch and gates.
448.​ Construct a hexadecimal up counter to count from 0 to 79H using minimum
asynchronous ICs and external gates.
449.​ Design a JK flip flop using a basic NAND latch and gates.
450.​ Construct a mod-42 decimal up counting circuit using only asynchronous ICs.
451.​ Design a T flip flop using a basic NOR latch and external gates.
452.​ A sequential circuit has two JK flip flops, A and B... Draw the logic diagram of the
circuit.
453.​ Design a sequential circuit with two D flip flops, A and B and one input x... (00 to 01
to 11 to 10 back to 00).
454.​ Design a 4 bit binary Up – DOWN counter.
455.​ Construct JK flipflop using D flipflop, 2 to 1 line mux and inverter.
456.​ Design sequential circuit for serial adder using JK flip flop.
457.​ Draw logic diagram of a 4 bit binary ripple down counter using flip flop that trigger on
positive edge of the clock.
458.​ Draw block diagram of 3 decade decimal BCD counter.
459.​ Explain Schmitt trigger.
460.​ Explain Monostable and Astable multivibrator.
461.​ Classify the shift registers. Explain any two of them with logical diagram.
462.​ Design a sequential circuit with two JK flip flops A and B and 2 inputs E and x...
463.​ Explain difference among truth table, state table, characteristic table and excitation
table.
464.​ Explain ring counter.
465.​ Design a BCD Ripple Counter using JK flip flops and discuss its construction.
466.​ Design a synchronous counter with the binary sequence 0, 1, 3, 2, 6, 4, 5, 7 using JK
flip-flop.
467.​ Design a mod-6 counter using JK flip-flop.
468.​ Design a self-correcting synchronous counter using T - flip flops... count the
sequence 1 → 4 → 6 → 3 → 2 → 1...
469.​ Using synchronous hexadecimal counter ICs and external gates, design a 2 - digit
hexadecimal down counter which counts from 94H to 35H and repeats.
470.​ Design a sequence generator to generate the sequence 1101011 by ring counter
using JK Flip flop.
471.​ Design synchronous divide by 10 counter using D-flip flops.
472.​ Design an asynchronous 4 - bit UP/ DOWN counter using negative edge triggered
JK - flip flops and minimum 2:1 multiplexer.
473.​ Design a sequence detector... sequence "1011" is detected... Implement using JK-
flip flops.
 474.​ Using a synchronous hexadecimal counter ICs and external gates, design a 2 - digit
hexadecimal counter which counts from 23 H to 56 H and repeats.
475.​ Using Johnson counter, generate the sequence 00011001. Use JK flip flops.
476.​ Design a self - correcting synchronous UP counter to count in 8 4 2 1 code using T -
flip flops.
477.​ Design an asynchronous Down counter to count from 5 to 2 using positive edge
triggered D - flip flops.
478.​ Using asynchronous hexadecimal counter ICs and external gates, design a 2 - digit
hexadecimal counter which counts from 00 to 89H and repeats.
479.​ Design and implement a MOD-5 synchronous counter using JK flip-flops and draw its
timing diagram.
480.​ Using asynchronous decade counter ICs and external gates, design a 2 - digit
decimal counter which counts from (00)10 to (86)10 and repeats.
481.​ Using ring counter, generate the sequence 01011. Use JK flip flops.
482.​ Design a self-correcting synchronous counter using T - flip flops... count the
sequence 1 → 3 → 2 → 5 → 4 →1...
483.​ Using Mealy model, write the state diagram for detecting the binary sequence 1101...
Overlapping allowed.

Topic VI: Computer Organization & Architecture

(Memory, Bus, Micro-operations, Addressing)

484.​ A given system has four sensors... Design the simplest logic circuit that can be used
to raise the alarm.
485.​ Consider the circuit in the following figure. Analyze the circuit and derive the
equations for the outputs x and y.
486.​ What are the different parts in Control Memory Data Buffer register in
microprogrammed approach for control unit design?
487.​ List and describe the different types of register microoperations.
488.​ What will be the output in the destination and source registers after execution of
each of the following instructions? (i) ROR R2, R1, #4 (ii) SHL (iii) SHRA (iv) ROLC.
489.​ Write the zero-address instructions for the given expression with register transfer
notations. X = (AB) + (CD).
490.​ Differentiate the various types of addressing modes with relevant examples.
491.​ Given the format of the control word, write the value of the control word for
performing the following operations. R1 <- R2 – R3, etc.
492.​ What are the different modes of data transfer between I/O devices and memory?
Explain.
493.​ Draw the architecture of a stack based machine and explain the functions of the
components involved in them.
​
​

494.​ Differentiate between RISC and CISC.

495.​ Identify the addressing modes and justify the same, for the following instructions. i)
HLT ii) MOV @#6000, R5.
496.​ Explain one bus, two bus and three bus oriented RALU with neat diagrams and an
example.
497.​ Design a 4-bit common bus system for 4-registers of 4-bits each using multiplexers.
498.​ With a neat diagram explain how data transfer between the registers takes place in a
computer system.
499.​ Explain different internal bus organization with necessary diagrams.
500.​ Explain the operation of a Direct Memory Access System.

501.​ Explain block transfer DMA technique with a neat diagram.

502.​ Explain daisy chain technique to handle multiple interrupts with the help of neat
diagram.
503.​ Develop bus architecture of the system based on tri-state buffer.
504.​ What is Direct Memory Access (DMA)? Explain the three different DMA data transfer
techniques.
505.​ Explain ROM, PROM and EPROM.
506.​ With a block diagram, explain the internal organization of a 64x4 RAM.

Topic VII: Computer Arithmetic Algorithms

(Booth's, CLA, Division, Floating Point)

507.​ Suppose 16-bit adder blocks are used for constructing a hierarchical carry look
ahead adder... then the total gate delay is ________.
508.​ Choose the true expression(s) for generating c3 in a carry-lookahead adder.
509.​ A system uses 16-bit unsigned integers. If X= 65520 and Y=50, what would be the
result of adding X and Y and how overflow should be handled?
510.​ For an 8-bit carry-lookahead adder where the delay per gate is 4ns... what is the
maximum delay?
511.​ Design a 4-bit by 3-bit binary multiplier and explain its operation.
512.​ Perform (12)x(7) using Booth’s multiplication.
513.​ A Binary multiplier is designed to multiply two numbers: (7)10 and (6)10. What is the
minimum required number of 4-bit adders to perform the multiplication?
514.​ A binary multiplier needs to be designed to multiply a 4-bit binary number by (1010).
What is the minimum number of AND gate and 4-bit parallel adders?
515.​ Perform (01101)base2 – (00111)base2 using 1’s complement method.
 516.​ In booth’s multiplication, how many subtraction operations are performed for the
multiplier (01101011)base 2.
517.​ Design a hierarchical 40-bit carry look-ahead adder with ripple-carry between 8-bit
blocks. Compute the total gate delay.
518.​ Design a circuit which generates the magnitude of a 5-bit signed number A[4:0] in
binary using half adders, multiplexers and NOT gates.
519.​ Draw the diagram for 3-bit array multiplier using full adders and half adders.
520.​ Design a 1-bit full adder with look - ahead carry.
521.​ Figure Q1A shows operation of 2-bit adder... Implement Half-adder and Full-adder
block using appropriate decoders.
522.​ Given M=17(10) and Q=-5(10). Multiply using Booth's algorithm.
523.​ Differentiate between restoring and non restoring division algorithms.
524.​ Write the flow chart for Booth's algorithm. Using the same perform multiplication of M
= 10(10) and Q = – 9(10).

525.​ Show the iterations involved in dividing 23(10) by 11(10) using restoring division
algorithm.
526.​ Perform 13 X 20 using Add and Shift method.
527.​ Perform 18 X -25 using Modified Booth’s algorithm.
528.​ Perform the following for 4 bit Add and Shift multiplication algorithm...
529.​ Design a 4 – bit x 4 – bit binary multiplier using full adders and external AND gates
ONLY.
530.​ Design a 4-bit binary Carry Look Ahead adder circuit. Discuss its merits over a 4-bit
binary ripple carry adder.

​
​

531.​ Divide 14(10) by 5(10) using restoring division algorithm indicating all the steps.
532.​ Why is non-restoring division algorithm preferred over restoring division algorithm?
Perform the division of (13)10 by (6)10 using the non-restoring division algorithm.
533.​ Divide 8/3 using the restoring division approach.
534.​ Design a 4-bit parallel adder with carry look ahead adder.
535.​ What is the role of the ALU (Arithmetic Logic Unit) in a CPU?
536.​ Multiply (-7)10 with (3)10 by using Booth's multiplication algorithm.
537.​ Perform (12)10 x (7)10 using Booth’s multiplication algorithm.
538.​ Design a 3 - bit binary Carry Look Ahead (CLA) adder circuit using logic gates.
539.​ Explain the concept of carry save adder with the help of an example.
540.​ Draw the flowchart of Non restoring division algorithm. Perform the division of (12)10
by (5)10.
541.​ Design a 4 bit binary adder using full adders and other gates and explain the
construction.
542.​ Explain the working of a Carry look ahead adder with relevant block diagrams.
 543.​ Draw the flowchart of booths multiplication algorithm. Perform the multiplication of
(15)10 by (7)10.
544.​ Explain the pros and cons of booths multiplication algorithm over add and shift
method.
545.​ Design a binary multiplier to multiply two, unsigned 3- bit numbers using minimum
external gates and 7483 ICs.
546.​ Carry save addition is faster that carry propagation addition (True/False). Justify.
547.​ Write the advantages and limitations of carry propagation adder, carry look ahead
adder and carry save adder.
548.​ Why is non restoring division algorithm more efficient than restoring division
algorithm? Divide (10101)2 by (110)2.
549.​ Draw and explain carry look ahead generator.
550.​ What is a look - ahead carry? Design and explain a 4-bit full adder with look - ahead
carry.

Topic VIII: Control Unit Design

(Hardwired, Microprogrammed)

551.​ Develop a hardware block diagram to perform following micro-operation.

552.​ Design a control unit of a simple processor to perform the operations mentioned in
Table below... Derive the expressions for all the control signals.
553.​ Develop the ASM chart for the bit counting circuit which counts the number of 1's in a
register.
554.​ Explain the elements of ASM chart with their symbols.
555.​ For the state diagram shown: Draw Micro programmed Control Unit, Write Micro
program, Determine Control Memory Size.

556.​ Calculate % Saving using Decoders only and by elimination of branch address.
557.​ Prove that Nano memory saves space of control memory.
558.​ List out the differences between two Priority interrupt handling techniques.
559.​ Design a hardwired control unit for 4x4 Booth's multiplier.
560.​ Explain the general purpose microprogrammed control unit design. How is it different
from hardwired design approach?
561.​ Design a microprogrammed control unit for 4x4 Booth's multiplier.
562.​ Design a microprogrammed control unit for 4 - bit x 4 - bit Booth's multiplier.
563.​ The control unit design using hardwired approach consists of...
564.​ Which signal is used to obtain control over the system bus for one clock cycle?
565.​ Design a hardwired control unit for 4x4 Booth’s multiplier.

Topic IX: Advanced Architectures

(Cache, FPGA, PLA/PAL, CMOS, Testing, ADC/DAC)

566.​ Implement an 8-to-1 multiplexer using an Altera MAX 7000 CPLD. Determine
macrocells required.
567.​ Realize the sequential circuit... using ACT 2C and ACT 2S logic modules.
568.​ Explain various types of programmable interconnects used in Xilinx XC 3000 with
neat diagram.
569.​ Implement functions using Xilinx XC 3000 FPGA. How many CLBs/LUTs required?
570.​ What is the size of the smallest ROM needed to implement: (a) A 4-to-1 MUX (b) An
8-to-3 priority encoder.
571.​ Find a minimum-row PLA table to implement functions x, y, z (minterms provided).
572.​ Explain SRAM and Anti-fuse programming technology.
573.​ Explain architecture of Xilinx Spartan FPGA.

574.​ Find minimum set of tests for stuck-at faults in Fig. Q5B.
575.​ Implement a full subtractor using PAL.
576.​ Explain the FPGA design flow.
577.​ Explain structure of CLB in Xilinx Spartan IIE.
578.​ Explain check point theorem. Determine inputs to test for faults in Fig. Q5A.
579.​ Explain architecture of ACTEL Axcelerator logic modules.
580.​ Explain Boundary scan test.
581.​ Explain the steps in Silicon processing.
582.​ Calculate average access time, ratio of main memory to cache, efficiency (specs
provided).
583.​ Determine hit ratio for FIFO and LRU (page stream provided).
584.​ With flow chart, Write note on FPGA Design flow.
585.​ Determine Size of tag field: Fully associative, Direct Mapping, Set associative.
586.​ Write the differences between Paging and Segmentation.
587.​ List CPLD/ FPGA programming technologies.
588.​ Using PROM of smallest size, draw logic diagram in PLD notation for F(X) = 3X +2.
589.​ Implement functions using suitable PLA.
590.​ Determine size of tag field (Main memory 4K blocks, Cache 512 blocks).
591.​ What is a combinational PLD? Differentiate three major types.
592.​ Implement the following functions using Xilinx FPGA... Show the interconnection
between various blocks. Specify the number of CLBs and LUTs required.
593.​ Given the state table of a sequential circuit as shown in Table 5A, implement it using
minimum number of ACT-2 S and ACT-2 C Module.
594.​ Define Programmable Logic Devices(PLDs). State four differences between the two
different types of PLDs.
595.​ Implement a 4-bit SISO register using Xilinx CLB.
596.​ Implement $F = \sum m (1,3,5,6)$ using ACT-1 module.
597.​ Explain the operation of SRAM Cell.
598.​ A two-way set-associative cache in a system with 24-bit addresses... (i) What is the
size of the main memory?
599.​ (i) Define associative mapping in the context of cache memory. (ii) How does
associative mapping differ from direct mapping?
600.​ With necessary diagrams, explain various cache mapping techniques.
601.​ Determine the tag field width of main memory address in each of cache memory
mapping technique.
602.​ With a neat diagram, explain the concept of master–slave flip flop.
603.​ Implement the following circuit using ACT-2 Sequential module.
604.​ Implement the following combinational circuit using Xilinx FPGA. Determine the
number of CLB's and LUT's required.
605.​ Explain ASIC Design.
606.​ How does a set associative cache mapping technique overcome the limitations of
fully associative and direct mapping techniques?
607.​ Explain Set Associative mapping in cache memory with the help of an example.
608.​ A Computer system has a 64K blocks of main memory and 8K blocks of cache
memory... Calculate the tag field width.
609.​ The parameters of a computer memory system are specified as follows: Main
memory size = 4K blocks... Determine the size of the tag field.
610.​ Design NAND gate using CMOS technology.
611.​ Implement full adder using ACT 1 logic module.
612.​ What is TTL logic? Explain the working of 2 input NAND gate using TTL logic.
613.​ Implement full subtractor using ACT-2 FPGA.
614.​ Explain the following gate parameters. a) Noise margin b) Propagation delay c) Fan
in.
615.​ Implement an 8-to-1 multiplexer using an Altera MAX 7000 CPLD.
616.​ (a) Find the controllability and observability at each line of the circuit in Fig. 2B. (b)
Draw the block diagram of ASIC design flow.
617.​ Explain various types of programmable interconnects used in Xilinx XC 3000 with
neat diagram.
618.​ Explain salient features of a set associative mapped cache memory.
619.​ Differentiate between direct and associative cache mapping techniques.
620.​ Following sets of Boolean functions are to be realized using 3 x 5 x 3 Programmable
Logic Arrays (PLA).
621.​ Tabulate PLA table for the following functions.
622.​ Write a brief note on PLA.
623.​ Realize the following Boolean functions using suitable ROM.
624.​ A Computer system has a 128 K of main memory and 4K of cache memory.
Calculate the tag field width for fully associative mapping, direct mapping and 4-way set
associative mapping schemes.
625.​ Assume a system’s memory has 128M words... What are the sizes of the tag, set,
and word fields?
626.​ With the help of neat diagrams, explain three different types of programmable logic
devices. Also, implement the following logic functions using suitable PLA.
627.​ Explain the working of Successive approximation ADC using a block diagram.
628.​ Explain the operation of a R/2R ladder DAC with a circuit diagram.
629.​ In the above circuit (DAC), assume that VREF = 5V what are the resolution and the
full scale output of the converter?
630.​ Explain the working of Successive approximation ADC using a block diagram.