GREATER NOIDA INSTITUTE OF TECHNOLOGY (GNIOT)

LABORATORY MANUAL

SUBJECT- COMPUTER ORGANIZATION & ARCHITECTURE LAB

SUBJECT CODE- BCS-352

SESSION- 2025-26 (ODD SEM)

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

GREATER NOIDA INSTITUTE OF TECHNOLOGY

APPROVED BY AICTE, NEW DELHI

ACCREDITED BY NAAC WITH A+ GRADE

PLOT NO. 7, KNOWLEDGE PARK - II GREATER NOIDA, U.P., INDIA

 Session: - 2025-26

Laboratory Manual
[Link]. Semester- III

Computer Organization & Architecture Lab

Subject code: - BCS-352

Prepared by: Checked by: Approved by:

Mohd. Imran Ansari

Sign.: ………………… Sign.: ………………. Sign.: …………………

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

GREATER NOIDA INSTITUTE OF TECHNOLOGY, GREATER

NOIDA, UP
 Table of Contents
1. Vision and Mission of the Institute
2. Vision and Mission of the Department
3. Programme Educational Objectives (PEOs)
4. Programme Outcomes (POs)
5. Programme Specific Outcomes (PSOs)
6. University Syllabus
7. Course Outcomes (COs)
8. CO- PO and CO-PSO mapping
9. List of Experiments

10. Concepts and solutions of experiments

11. Value Addition Lab Experiments

12. References
 Institute Vision and Mission

Vision of Institute
“Be known globally for value-added education, innovation, and research at the
intersection of disciplines in service of humankind.”

Mission of Institute

M-1: Place a multidisciplinary engineering education ecosystem that transforms

learners into future innovators, entrepreneurs, and professional leaders.

M-2: Create an ambiance of interdisciplinary research, innovation, and creativity to

address regional and global challenges for benefit of human life and the environment.

M-3: Provide the environment for enhancing knowledge, and inculcating critical &
design thinking, life skills through quality learning systems.

M-4: Collaborate with globally renowned academic & research institutions and
corporates for improving productivity and economics.
 Department of Computer Science & Engineering

Vision, Mission & PEOs

Vision of the Department:

To produce Computer Science and Engineering graduates with problem-solving

abilities, research aptitude, teamwork, and ethical values to meet the needs of industry
and society.

Mission of the Department:

M1: To prepare students with strong technical skills and analytical minds for real time
industrial needs.
M2: To nurture the students to contribute in research and innovation for nation
building.
M3: To develop students with leadership qualities to be entrepreneurs and contribute
their services to society.

PEOs:

● PEO-1: Prepare graduates to have knowledge and competency for careers related
to Computer Science.
● PEO-2: Prepare graduates to become leaders in fields related to Computer
Science.
● PEO-3: Prepare graduates to pursue higher education in Engineering or other
Professional fields.
● PEO-4: Prepare graduates to apply contextually informed reasoning to evaluate
societal, health, safety, legal, and cultural issues.
 Programme Outcomes (Pos)
Program
Statement
Outcome
PO1 Engineering knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering specialization to the solution
of complex computer engineering problems.
PO2 Problem analysis: Identify, formulate, review research literature, and
analyze complex computer engineering problems reaching substantiated
conclusions using first principles of mathematics, natural sciences, and
engineering sciences.
PO3 Design/development of solutions: Design solutions for complex computer
engineering problems and design system components or processes that
meet the specific needs with appropriate considerations for the public
health and safety, and the cultural, societal, and environmental
considerations.
PO4 Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide
conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and
the consequent relevant to the professional engineering practices.
PO7 Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts,
and demonstrate the knowledge of, and need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norm of the engineering practices.
PO9 Individual and team work: Function effectively as an individual, and as
a member or leader in diverse teams, and in multidisciplinary settings.
PO10 Communications: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such
as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions.
PO11 Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply
these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
PO12 Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life learning in the broadest context of
technological change.
 Programme Specific Outcomes (PSOs)

After completing their graduation, students of Computer Science and Engineering will
be able to do:

Programme
Specific
Statement
Outcomes
(PSO)

Acquire expertise in CSE subjects to empower students to develop solutions

PSO1
for the betterment of humankind.
Extrapolate fundamental engineering concepts and apply cutting-edge
PSO2 technology and programming language skills to develop, test, implement,
and maintain software products.
University Syllabus
 Course Outcomes (COs)
At the end of the course, the student will be able to:

CO Course Outcome Bloom’s Knowledge

Level (KL)
CO1 Design addition, comparison, and decision-making circuits.
K₂, K₄

CO2 Design various combinational circuits like MUX, Decoder etc. K₃, K₅

CO3 Implement the I/O and memory organization by using various sequential K₄, K₃
circuits.

CO4 Understand the performance and issues of various computer K₄, K₅

organizations.

CO5 Apply control unit functions using microprogramming or hardwired K₃, K₄

approach on the basis of register transfer language.

CO-PO and CO-PSO Mapping

Course Code CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 3 2 3 - 2 - - - - - - 1 3 2

BCS352 CO2 3 2 3 - 2 - - - - - - 1 3 2

CO3 3 2 3 - 2 - - - - - - 1 3 2

CO4 2 3 1 - 1 - - - - - - 1 2 1

CO5 3 2 3 - 2 - - - - - - 1 3 2

- - - - -
Mapping Strength 2.8 2.2 2.6 - 1.8 - 1.0 2.8 1.8
(Avg)
 CO-PO Justification

CO No. PO Justification
3 Designing arithmetic and decision circuits demands strong
PO1 application of mathematics, logic, and computer engineering
fundamentals.

2 Requires analysing functional requirements and constraints before

PO2 selecting circuit implementations.

3 Direct design of digital circuits such as adders, comparators, and

PO3 decision logic is a core design and development activity.

2 Realization and verification typically use electronic design

PO5 automation tools or digital circuit simulation software, indicating
CO1 moderate tool usage.

1 Encourages independent learning of logic concepts and datasheets,

PO12 but not a major emphasis.

3 Builds strong computer science and engineering hardware

PSO1 expertise through core digital design competencies.

2 Applies foundational concepts and, where used, hardware

PSO2 description language or programming skills to implement and test
circuits.

3 Combinational design such as multiplexers and decoders relies

PO1 heavily on computer engineering fundamentals and Boolean
algebra.

2 Involves requirement analysis, truth-table derivation, and

PO2 minimization decisions.
3 Explicitly a design and development course outcome for standard
CO2 PO3 combinational blocks.
2 Moderate use of design and simulation tools to validate
PO5 multiplexer and decoder behaviour.
1 Slight emphasis on self-learning of device characteristics and
PO12 integrated circuit families.
 3 Strengthens domain expertise in digital logic design for computer
PSO1 science and engineering.
2 Applies engineering concepts and basic programming or hardware
PSO2 description language skills for implementation and testing.
3 Implementing input/output and memory with sequential circuits
PO1 uses deep computer engineering fundamentals and timing theory.
2 Requires analysing timing, state behaviour, and organization trade-
PO2 offs.

3 Substantial design work to realize sequential subsystems and

PO3 memory organization.

2 Moderate reliance on hardware description language, simulation

PO5 software, or assemblers for validation.
CO3
1 Slight emphasis on independent study of memory and input/output
PO12 standards and datasheets.

3 Deepens computer science and engineering expertise in computer

PSO1 organization and memory systems.

2 Applies core engineering concepts and implementation skills to

PSO2 build and test sequential subsystems.

2 Understanding performance and issues draws on computer

PO1 engineering fundamentals but the focus is analysis rather than
construction.

3 High-level problem analysis to diagnose performance bottlenecks

PO2 and architectural issues.

1 Only slight design involvement, for example minor modifications

PO3 for improvement; primary focus is analysis.

1 Slight use of measurement, profiling, or simulation tools to study

CO4 PO5 performance.

1 Slight emphasis on learning new performance-analysis techniques

PO12 independently.

2 Moderately contributes to computer science and engineering

PSO1 expertise via organization and performance understanding.

1 Slight link to applying technology; primarily conceptual and

PSO2 performance analysis rather than implementation.
 Control-unit design, whether register transfer language based,
PO1 3 hardwired, or microprogrammed, uses strong computer
engineering fundamentals and state-machine theory.

Requires analysing control requirements and instruction behaviour

PO2 2 to derive control signals.

Synthesis of control logic and microprograms is a major design

PO3 3 activity.

Moderate use of hardware description language, assembler

PO5 2 programming, or microprogramming tools for modelling and
CO5
verification.

Slight emphasis on self-directed learning of register transfer

PO12 1 language and microprogramming concepts.

Builds advanced computer science and engineering hardware

PSO1 3 competence via control-unit realization.

Applies programming, hardware description language, or

PSO2 2 microprogramming skills to implement and test control behaviour.
 List of Experiments (BCS352)
S. No. Name of Experiments CO(s)
1 To Study and verify the Truth Tables of various logic gates. CO1
2 Implementing HALF ADDER, FULL ADDER using basic logic gates. CO2
3 Implementing Binary -to -Gray, Gray -to -Binary code conversions. CO2
4 Implementing 4x1 MULTIPLEXERS. CO2
5 Implementing 8x1 MULTIPLEXER using 2X 1 MULTIPLEXER. CO2
6 Implementing 3–8-line DECODER. CO2

7 Verify the excitation tables of various FLIP-FLOPS. CO3

8 Design of an 8-bit Input/ Output system with four 8-bit Internal Registers. CO4
9 Design of an 8-bit ARITHMETIC LOGIC UNIT. CO4
10 Design the data path of a computer from its register transfer language description CO5

11 Design and implement a BCD Adder. CO4

12 Implementing Incrementer circuit using half adder. CO2
13 Implementing Deccrementer circuit using full adder. CO2
14 Design and Implementation of SISO and SIPO shift registers. CO5
15 Design and Implementation of PISO and PIPO shift registers. CO5

Value added Laboratory Experiment(s): -

S. No. Name of Experiments CO(s)

1 Assembling of parts of a computer: Motherboard, Processor, RAM, Hard Disk, CO4
SMPS, and I/O devices.
2 Acquainted with the parts of computers: Motherboard, Processor, RAM, Hard Disk, CO4
SMPS and I/O devices.
3 Implementing half subtractor using basic logic gates. CO2
4 Implementing full subtractor using basic logic gates. CO2
5 To design a 4-bit adder subtractor. CO4
 EXPERIMENT No.-1

AIM: To study and verify the truth tables of various logic gates.

Software Used: Circuitverse Online Simulator/Logisim

BRIEF THEORY: Logic gates are idealized or physical devices implementing a Boolean function,
which it performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise
time and unlimited fan out or it may refer to a non-ideal physical device.

The main hierarchy is as follows:

1. Basic Gates
2. Universal Gates
3. Advance Gates
Basic Gates:
1. AND gate: The AND gate plays an important role in the digital logic circuit. The output state of the
AND gate will always be low when any of the inputs states is low. Simply, if any input value in the AND
gate is set to 0, then it will always return low output (0).

The logic or Boolean expression for the AND gate is the logical multiplication of inputs denoted by a
full stop or a single dot as
Y=A.B

Result:
2. OR gate: The OR gate is a mostly used digital logic circuit. The output state of the OR gate will
always be low when both of the inputs states is low. Simply, if any input value in the OR gate is set to
1, then it will always return high-level output(1).
The logic or Boolean expression for the OR gate is the logical addition of inputs denoted by plus
sign(+) as
Y=A+B

Result:
3. NOT gate: The NOT gate is the most basic logic gate of all other logic gates. NOT gate is also known as
an inverter or an inverting Buffer. NOT gate only has one input and one output. When the input signal is
"Low", the output signal is "High" and when the input signal is "High", the output is "Low".
The Boolean expression for the NOT gate is as follows:
A'=Y

Result:
Universal Gates

1. NAND gate: The NAND gate is a special type of logic gate in the digital logic circuit. The NAND
gate is the universal gate. It means all the basic gates such as AND, OR, and NOT gate can be
constructed using a NAND gate. The NAND gate is the combination of the NOT-AND gate. The
output state of the NAND gate will be low only when all the inputs are high. Simply, this gate returns
the complement result of the AND gate.
The logic or Boolean expression for the NAND gate is the complement of logical multiplication of
inputs denoted by a full stop or a single dot as
(A.B)'=Y

Result:

2. NOR gate: - The NOR gate is also a universal gate. So, we can also form all the basic gates using
the NOR gate. The NOR gate is the combination of the NOT-OR gate. The output state of the NOR
gate will be high only when all of the inputs are low. Simply, this gate returns the complement result
of the OR gate.
The logical or Boolean expression for the NOR gate is the complement of logical multiplication of
inputs denoted by the plus sign as
(A+B)'=Y

Result:
Advanced Gates

XOR gate: The function of XOR gate is to give output true only when the number of 1’s in inputs is
odd.

Y=(A⨁B)
Y=(A' B+AB')

Result:

XNOR gate: The exclusive-NOR is the complement of the exclusive-OR, as indicated by the small
circle in the graphic symbol. The output of this gate is 1 only if both inputs are equal to 1 or both
inputs are equal to 0.
Y=(A⨁B)'
Y=((AB)'+AB)

Result:

All gates are verified. Observed output matches theoretical concepts.

 EXPERIMENT No.-2

AIM: - Implementing HALF ADDER, FULL ADDER using basic logic gates.

Software Used: Circuitverse Online Simulator/Logisim

BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logic operation but
ALU doesn’t perform/ process decimal no’s. They process binary no’s.

Half Adder: It is a logic circuit that adds two bits. It produces the O/P, sum & carry. The Boolean
equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1. Application of Half
adder is limited.
Full Adder: It is a logic circuit that can add three bits. It produces two O/P sum & carry. The Boolean
Equation for sum & carry are:
SUM = A + B + C
CARRY = A.B + (A+B) C
Therefore, sum produces one when I/P is containing odd no’s of one & carry is one when there are two
or more one in I/P.

LOGIC DAIGRAM:

Half Adder Full Adder

OBSERVATION TABLES:

HALF ADDER:
INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER:
INPUTS OUTPUT
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

RESULT:

Half Adder:
Full Adder:
The Half Adder & Full Adder circuits are verified.

VIVA QUESTIONS
1. Give the basic rules for binary addition? 0+0 = 0; 0+1 =
1; 1+1 = 1 0; 1+0 = 1.

2. Specify the no. of I/P and O/P of Half adder? Two inputs
& one output.

3. What is the drawback of half adder?

We can’t add carry bit from previous stage.

4. Write the equation for sum & carry of half adder? Sum =
A XOR B; carry = A.B.

5. Write the equation for sum & carry of full adder?

SUM= A’B’C+A’BC’+AB’C’+ABC; CARRY=AB+BC+AC.
 EXPERIMENT No.-3

AIM: Implementing Binary -to -Gray, Gray -to -Binary code conversions.

Software Used: Circuitverse Online Simulator/Logisim

BRIEF THEORY: The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital system. It is sometimes necessary to
use the output of one system as the input to another. A conversion circuit must be inserted between the
two systems if each uses different codes for the same information. Thus, a code converter is a circuit
that makes the two systems compatible even though each uses a different binary code.

Logic diagram:
Binary to Gray Code Gray to Binary Code
Truth Table:

Binary Code Gray Code

Result:
Binary-to-Gray Code Circuit:
Gray-to-Binary Code circuit:

The Binary-to-Gray & Gray-to-Binary code convertor circuits are verified.

 EXPERIMENT No.-4

AIM: Implementing 4x1 and 8x1 MULTIPLEXERS.

Software Used: Circuitverse Online Simulator/Logisim
BRIEF THEORY:

MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is a circuit with many
Inputs but only one output. By applying control signals we can steer any input to the output. The circuit
has n-input signal, control signal & one output signal. Where 2n = m. One of the popular multiplexers
is the 16 to 1 multiplexer, which has 16 input bits, 4 control bits & 1 output bit.

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the output. The block diagram and the
truth table of the 4×1 multiplexer are given below.

Block Diagram: Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer:
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3 selection
lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0, S1, and S2, one of these 8 inputs are connected to the output. The block
diagram and the truth table of the 8×1 multiplexer are given below.
Block Diagram: Truth Table:
The logical expression of the term Y is as follows:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1
.S3.A7
Logical circuit of the above expression is given below:

RESULT:
4 X 1 MUX:
8 X 1 MUX:

Result:

The 4 X 1 & 8 X 1 Multiplexers circuits are verified.

 EXPERIMENT No.-5 (Part B of 4th Experiment)

AIM: Implementing 8x1 MULTIPLEXER using 2X1 Multiplexer.

Software Used: Circuitverse Online Simulator/Logisim
BRIEF THEORY:

Larger Multiplexers can be constructed by using lower multiplexers by chaining them together. For
illustration, an 8:1 multiplexer can be formed with 2:1 multiplexer.
 EXPERIMENT No.-6
AIM: Implementing 3–8-line DECODER

3-8 LINE DECODER

BRIEF THEORY:
3-8 LINE DECODER is designed to be used in high-performance memory-decoding or data routing
applications requiring very short propagation delay times. In high-performance memory systems, this
decoder can be used to minimize the effects of system decoding. When employed with high-speed
memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the
memory are usually less than the typical access time of the memory. This means that the effective system
delay introduced by the decoder is negligible. The conditions at the binary-select (A, B, C) inputs and
the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two active-low and one active-
high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder
can be implemented without external inverters and a 32-line decoder requires only one inverter. An
enable input can be used as a data input for demultiplexing applications.

3-to-8-line decoder: The 3-to-8-line decoder is also known as Binary to Octal Decoder. In a 3-to-8-line
decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e.,
A0, A1, and A2. This circuit has an enable input 'E'. Just like 2-to-4-line decoder, when enable 'E' is set
to 1, one of these four outputs will be 1. The block diagram and the truth table of the 3-to-8-line decoder
are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2'

Y1=A0.A1'.A2'

Y2=A0'.A1.A2'

Y3=A0.A1.A2'

Y4=A0'.A1'.A2

Y5=A0.A1'.A2

Y6=A0'.A1.A2

Y7=A0.A1.A2
Logical circuit of the above expressions is given below:
 EXPERIMENT No.-7
AIM: Verify the excitation tables of various FLIP-FLOPS.

BRIEF THEORY:
SR FLIP FLOP:

RESULT: Truth table is verified on digital trainer.

VIVA QUESTIONS

[Link] flop is Astable or Bistable? Bistable.

[Link] is the I/Ps of JK flip–flop where this race round condition occurs? Both the inputs
are 1.

[Link] RS flip-flop is said to be in a SET state? When the output

is 1.

[Link] RS flip-flop is said to be in a RESET state? When the output

is 0.
 EXPERIMENT No.-8
AIM: Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

BRIEF THEORY:
A universal shift register is an integrated logic circuit that can transfer data in three different modes.
Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and
transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register
can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic
type of register can perform on its own. For instance, on a particular job a universal register can load
data in series (e.g., through a sequence of left shifts) and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as memory elements.
Although other types of memory devices are used for the efficient storage of very large volume of data,
from a digital system perspective when we say computer memory, we mean registers. In fact, all the
operations in a digital system are performed on registers. Examples of such operations include
multiplication, division, and data transfer.
In order for the universal shift register to operate in a specific mode, it must first select the mode. To
accomplish mode selection the universal register uses a set of two selector switches, S1 and S0.

Operating Mode S1 S0

Locked 0 0

Shift-Right 0 1

Shift-Left 1 0

Parallel Loading 1 1

LOGIC DIAGRAM:
The transfer of information from a bus into one of many destination registers can be accomplished by
connecting the bus lines to the inputs of all destination registers and activating the load control of the
particular destination register selected. The symbolic statement for a bus transfer may mention the bus
or its presence may be implied in the statement. When the bus is includes in the statement, the register
transfer is symbolized as follows:
BUS ← C, R1 ← BUS

The content of register C is placed on the bus, and the content of the bus is loaded into register R1 by
activating its load control input. If the bus is known to exist in the system, it may be convenient just to
show the direct transfer.
R1 ← C

From this statement the designer knows which control signals must be activated to produce the
transfer through the bus.
 EXPERIMENT No.-9
AIM: Design of an 8-bit ARITHMETIC LOGIC UNIT.

BRIEF THEORY:
The arithmetic microoperations can be implemented in one composite arithmetic circuit. The basic
component of an arithmetic circuit is the parallel adder. By controlling the data inputs to the adder, it is
possible to obtain different types of arithmetic operations. It has four full-adder circuits that constitute
the 4-bit adder and four multiplexers for choosing different operations. There are two 4-bit inputs A and
B and a 4-bit output D. The four inputs from A go directly to the X inputs of the binary adder. Each of
the for inputs from B are connected to the data inputs of the multiplexers. The multiplexer’s data inputs
also receive the complement of B. The other two data inputs are connected to logic-0 ad logic -1. Logic-
0 is fixed voltage value (0 volts for TTL integrated circuits) and the logic-1 signal can be generated
through an inverter whose input is 0. The four multiplexers are controlled by two selection inputs, S1
and S0. The input carry Cin goes to the carry input of the FA in the least significant position. The other
carries are connected from one stage to the next. The output of the binary adder is calculated from the
following arithmetic sum:
D = A + Y + Cin

Where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at the Y inputs of
the binary adder. Cin is the input carry, which can be equal to 0 or 1. Note that the symbol + in the
equation above denotes an arithmetic plus. By controlling the value of Y with the two selection inputs
S1 and S0 ad making Cin equal to 0 or 1, it is possible to generate the eight arithmetic micro-operations.

When S1 S0 = 00, the value of B is applied to the Y inputs of the adder. If Cin = 0, the output
D = A + B. If Cin = 1, output D = A + B + 1. Both cases perform the add microoperation with or without
adding the input carry.
When S1 S0 = 01, the complement of B is applied to the Y inputs of the adder. If Cin = 1, then D =A
+B+ 1. This produces A plus the 2’s complement of B, which is equivalent to a subtract with borrow,
that is, A – B – 1.

LOGIC DIAGRAM:

When S1S0 = 10, the input from B are neglected, and instead, all 0’s are inserted into the Y inputs. The
output becomes D = A + 0 +Cin. This gives D = A when Cin = 0 and D = A +1 when Cin =1. In the first
case we have a direct transfer from input A to output D. In the second case, the value of A is incremented
by 1.
When S1 S0 = 11, all 1’s are inserted into the Y inputs of the adder to produce the decrement operation
D = A –1 when Cin. This is because a number with all 1’s is equal to the 2’s complement of 1 (the 2’s
complement of binary 0001 is 1111). Adding a number A to the 2’s complement of 1 produces F = A
+2’s complement of 1 = A – 1. When Cin = 1, then
D = A – 1 + 1 =A, which causes a direct transfer from input A to output D. Note that the microoperation
D = A is generated twice, so there are only seven distinct microoperations in the arithmetic circuit.
 EXPERIMENT No.-10
AIM: Design the data path of a computer from its register transfer language description.

BRIEF THEORY:
This data path circuit to be built requires several components that we will design and implement and
test individually. To facilitate successful implementation, verification and documentation of complex
designs, one should proceed in an incremental, modular fashion whereby each component of a circuit
is built and verified independently. The components are then put together and may form another, larger
component at the next level of the design hierarchy.
These combined components may then be combined to from even larger components and so on. This
continues to the top level of the design. This practice applies to the design of hardware, software or any
other system for that matter! Our final goal here is to design and implement the logic for a hardware
data path that contains a simple arithmetic and logic unit (ALU) that can perform low level processing.

Step 1 Decoder
The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one HI‐true enable input as
shown in the circuit of Step 4. This is similar to the decoder you designed in a previous lab. Implement
this component using the graphic design editor and test it in the MAX7000 device.

Step 2 Quad 4:1 MUX

The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX has four 4‐bit data

inputs, a 4‐bit data output and two select lines as shown below. Study the VHDL source code given at
the end of this lab that implements a Quad 4:1 multiplexer. Be sure you understand the logic of the
VHDL code. Compile this program, implement and test using the MAX7000 device. Generate a symbol
for this MUX which you will use later.

Step 3 Registers
The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the VHDL
code at the end of this lab. Each register comprises 4 positive edge‐triggered D flipflops. Each register
has a 4‐bit input data and a 4‐bit output data. The clock input to all flipflops in the register is defined as
Clk. Compile this code and make a symbol for the register.
Step 4 Register File
Now we will design the register file using the graphic design editor by connecting the multiplexer,
decoder and four registers as shown below. Compile and test the register file circuit in the MAX7000
chip to ensure that all four registers can be loaded using toggle switches on the
Data In lines, and read using LEDs connected at the Data Out lines. Be sure that you understand the
timing of the "load enable" input relative to all the other inputs and outputs.

Step 5 Datapath
The register file forms the basis of a "data path" which is a fundamental building block of a computer.
See the diagram below. Data is selected from any register then stored back into any other register in the
register file, all in a single clock cycle (a lo‐hi‐lo pulse applied to the load enable LE input). A Quad 2:1
MUX included as shown below allows external data to be inserted into the data path. Data can thus be
transferred between any two registers of our register file or any register can be loaded with external
data. This data path can execute the following operations:

(a) any register can be loaded with external data from switches Rd ← data (4‐bits) (where
d=0,1,2 or 3)
(b) any register can be loaded with the data contained in any one of the other registers, including
itself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3) The implementation is shown
below. The inputs [ D1, D0, S1, S0, DS] form a 5‐bit "control" word which specifies the source (S1,
S0) and destination (D1, D0) registers of the register file and an operation (DS) that is to take place.
For DS=0, external data from switches is loaded into the destination register; for DS=1, data is
transferred from the source register to the destination register. Once the control word and data input
(if appropriate) are set on the level switches, execution is achieved by applying a load enable (LE)
input to the register file. This LE input may be considered as the clock to the entire system. You can
view the results of each operation using four LEDs connected to the output of the register file as
shown. Design this data path using the graphic design editor. VHDL code for the Quad 2:1 MUX
design is given at the end of this lab. Test the circuit for various combinations of the register transfers
summarized in the following table.

Summary of register transfer operations:

Note: (1) the first four lines of this table allow for initializing the register contents (DS = 0).
(2) this is not a complete table of all possible microoperations that can execute
 EXPERIMENT No.-11
AIM: Design and implement a BCD Adder.

THEORY:
4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must
be represented in BCD and should appear in the form listed in the columns.
A BCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:BCD ADDER
 Y = S4 (S3 + S2)

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.
 EXPERIMENT No.-12
AIM: Implementing Incrementer circuit using half adder

BRIEF THEORY:

It adds 1 binary value to the existing binary value stored in the register or in other words we can
simply say that it increases the value stored in the register by 1.
For any n-bit binary incrementer, ‘n’ refers to the storage capacity of the register which needs to
be incremented by 1. So, we require ‘n’ number of half adders. Thus, in case of 4-bit binary
incrementer we require 4 half adders.

Working:
• The half adders are connected one after the other, as it has 2 inputs and 2 outputs, so
for the LSB (least significant bit) half adder or the right most half adder is given 1 as
direct input (first input) and A0 which is the first bit of the register (second input), so
we get the two outputs: sum (S0) and carry (C).
• The carry(C) from previous half adder is propagated to the next half adder, so the carry
output of the previous half adder becomes the input of the next higher order half adder.
• So, considering the case for 4 half adders the circuit gets in total 4 bits (A0, A1, A2,
A3), 1 is added and we get an incremented output.
 EXPERIMENT No.-13
AIM: Implementing Decrementer circuit using full adder

4 Bit Binary Decrementer:

It subtracts 1 binary value from the existing binary value stored in the register or in other words
we can simply say that it decreases the existing value stored in the register by 1.
For any n- bit binary decrementer, ‘n’ refers to the storage capacity of the register which needs to
be decremented by 1. So, we require ‘n’ number of full adders. Thus, in case of 4-bit binary
decrementer we require 4 full adders.

Working:
• It consists of 4 full adders, connected one after the other. Each full adder has 3 inputs
(carry input, 1, A) and 2 outputs (carry output and S)
• A full adder basic consists of 2 half adders and an OR gate.
• The carry(C) from previous full adder is propagated to the next full adder. So, carry
output from one full adder becomes one of the three inputs of the next full adder.
• It follows the concept of 2’s complement, so we take 1 as input in all 4 full adders as
seen from the above diagram.
• So, we add 1111 in order to subtract 1.
Reason for adding 1111:

• This is because our main motive is to subtract 1 which in 4-bit representation is 0001
• Representing it in 1’s complement will give: 1110
• Representing it in 2’s complement (adding 1 to 1’s complement) will give: 1111
• This is the reason why input 1111 is given to get a decremented output in 4-bit binary
decrementer.
 EXPERIMENT No.-14
AIM: Design and Implementation of SISO and SIPO shift registers
 EXPERIMENT No.-15
AIM: Design and Implementation of PISO and PIPO shift registers.
 Value added Laboratory Experiment(s)

EXPERIMENT No.-1
AIM: Assembling of parts of a computer: Motherboard, Processor, RAM, Hard Disk, SMPS,
and I/O devices.

Assembling a computer involves connecting various components to create a functional system.

Here's a step-by-step guide on how to assemble the parts you've mentioned:
Tools You'll Need:

• Phillips screwdriver
• Anti-static wrist strap (optional but recommended)

Components:

1. Motherboard
2. Processor (CPU)
3. RAM
4. Hard Disk (HDD/SSD)
5. SMPS (Switched-Mode Power Supply)
6. I/O Devices (keyboard, mouse, monitor)

Assembly Steps:

1. Prepare Your Workspace:

o Make sure you have a clean, flat surface to work on.
o Ground yourself to prevent static discharge.
2. Install the CPU:
o Open the CPU socket lever on the motherboard.
o Align the CPU with the socket (look for the triangle indicator) and gently place it
into the socket.
o Close the lever to secure the CPU.
3. Attach the CPU Cooler:
o If your CPU cooler has thermal paste pre-applied, you can directly install it. If not,
apply a small amount of thermal paste on the CPU.
o Secure the cooler according to its instructions, usually with clips or screws.
4. Install the RAM:
o Locate the RAM slots on the motherboard.
o Open the clips on the slots.
o Align the notch on the RAM module with the slot and press down firmly until it
clicks into place. Repeat for additional RAM sticks.
5. Prepare the Case:
o Open the computer case and install standoffs if necessary to hold the motherboard.
o Ensure the I/O shield is in place on the back of the case.
6. Install the Motherboard:
o Align the motherboard with the standoffs and I/O shield.
o Secure it with screws.
7. Install the Hard Disk:
o Mount the HDD/SSD in the appropriate drive bay.
o Connect it to the motherboard using SATA cables.
 8. Install the SMPS:
o Place the SMPS into the designated area in the case (usually at the bottom or top).
o Secure it with screws.
9. Connect Power Cables:
o Connect the 24-pin ATX power cable from the SMPS to the motherboard.
o Connect the CPU power cable (usually 4 or 8 pins).
o Connect power cables to the HDD/SSD.
10. Connect I/O Devices:
o Connect the keyboard and mouse to the USB ports.
o Connect the monitor to the appropriate port (HDMI, DisplayPort, etc.).
11. Final Checks:
o Ensure all connections are secure.
o Check that all components are correctly installed and not touching any metal parts
of the case.
12. Power On:
o Connect the power cable to the SMPS and turn it on.
o Power on the monitor and the computer.
o If everything is correctly assembled, you should see the boot screen.

Troubleshooting:

• If the computer doesn’t power on, check all connections and ensure the power supply switch
is on.
• Listen for any beep codes which can indicate hardware issues.

Conclusion:
Congratulations on assembling your computer! Once it powers on successfully, you can proceed to
install the operating system and drivers. Enjoy your new build!
 EXPERIMENT No.-2
AIM: Acquainted with the parts of computers: Motherboard, Processor, RAM, Hard Disk,
SMPS and I/O devices.

Here’s a brief overview of each part of a computer and its function:

1. Motherboard:

• Description: The main circuit board that connects all components of a computer.
• Function: It houses the CPU, RAM, and other essential components, providing pathways
for communication between them. It also includes ports for connecting I/O devices and
expansion slots for additional hardware.

2. Processor (CPU):

• Description: The central processing unit, often referred to as the brain of the computer.
• Function: It performs calculations, processes instructions, and manages data flow between
other components. The CPU's performance greatly influences overall system speed.
3. RAM (Random Access Memory):

• Description: Temporary memory used for storing data that is actively being used or
processed.
• Function: It allows for quick read and write access to data, enabling faster performance
during tasks. When the computer is powered off, RAM loses its data.

4. Hard Disk (HDD/SSD):

 • Description: Storage devices used to hold data and applications.
o HDD (Hard Disk Drive): Uses spinning disks to read/write data.
o SSD (Solid State Drive): Uses flash memory for faster access speeds.
• Function: Provides long-term storage for the operating system, software, and files. SSDs
offer better performance compared to traditional HDDs.

5. SMPS (Switched-Mode Power Supply):

• Description: The component that converts electrical power from an outlet into usable power
for the computer's components.
• Function: Supplies power to the motherboard, CPU, and other components, ensuring they
receive the correct voltage and current.

6. I/O Devices

• Description: Input/Output devices used to interact with the computer.

• Examples:
o Input Devices: Keyboard, mouse, microphone.
o Output Devices: Monitor, printer, speakers.
• Function: Allow users to input data into the computer and receive output from it, facilitating
interaction with the system.

Summary
Each part plays a crucial role in the overall functioning of a computer, working together to perform
tasks and provide a user-friendly experience.
 EXPERIMENT No.-3
AIM: Implementing half subtractor using basic logic gates.
SCHEMATIC DIAGRAM:
 EXPERIMENT No.-4
AIM: Implementing full subtractor using basic logic gates.

TRUTH TABLE:
RESULT: The output waveform of full subtractor is verified.
 EXPERIMENT No.-5
AIM: To design a 4-bit adder subtractor.
RESULT: The circuit of a 4-Bit adder subtractor is designed and verified.