Future Digital system II lecture Notes

university
Lecture No (7)
Sequential Logic Circuits
Introduction
In combinational circuits the output depends only on
the condition of the present inputs.
In sequential circuits the output depends not only on the present inputs, but also on the
condition of earlier inputs.

Sequential circuits
Sequential circuits can be categorized as being
a. synchronous
b. Asynchronous.
A synchronous sequential circuit usually has a clock pulse (clocked sequential
circuits).

Sequential logic circuits with a periodic ―clock‖

signal
 Future university Digital system II lecture Notes

Latches and Flip-flops

Basic sequential circuits are latches and Flip-flops which have two stable states of
complementary output values.
Latches are a sequential device that checks all of its inputs continuously and changes its
outputs accordingly independent of a clocking signal.
Flip flops are storage elements that normally samples its inputs and changes its outputs only
at
times determined by clocking signal.
Latches:
The latch is a type of temporary storage device that has two stable states (bistable) and is
normally placed in a category separate from that of flip-flops.
Latches are similar to flip-flops because they are bistable devices that can reside in either of
two
states using a feedback arrangement, in which the outputs are connected back to oposite inputs.
The main difference between latches and flipflops is in the method used for changing their states.
The S-R (SET-RESET) Latch
A latch is a type of bistable logic device or multivibrator. An active-HIGH input S-R (SET-
RESET) latch is not formed with two cross-coupled NOR gates, as shown in figure. 1(a); an
active-LOW input S  R Latch is formed with two cross-Coupled NAND gates, as shown in
figure. 1(b). Notice that the output of each gate is connected to an input of the oposite gate.
This produces the regenerative feedback that is characteristic of all latches and flipflop.

(a) active-HIGH input S-R (b) active-LOW input S  R

latch Latch
Future university Digital system II lecture Notes

The S-R (Active HIGH input) Latch

An RS latch is a memory element with 2 inputs: Reset (R) and Set (S) and 2 outputs: Q and Q .
Q = 1 (Q = 0) represents the set state and Q = 0 (Q = 1) represents the reset state.
The S-R latch can be implemented by NOR gates or NAND gates.

NOR gate
Truth implementation
table

Assume S=1 and R=0, the output of the bottom gate (Q) is 0. The output of the top
gate
(Q) is 1. This is the set state. After the above state, Assume S becomes 0. From the previous
state Q =1, the output of the bottom gate stays at 0 the output of the top gate also stays at 1.
if S=0 and R=1, then Q=0 and Q =1. This is the reset state. Again, if R becomes 0 right after
the reset state, the outputs will remain unchanged (Q=0 and Q‘=1). In undefined state the
next output is not predictable when both inputs go back to zero (it depends whether the S or
R input goes to zero first).
Future university Digital system II lecture Notes

The Gated D Latch

D latch (data latch) is an element which holds data in its internal storage and the
output becomes equal to D each time C enables the circuit (by changing to 1).

Circuit diagram of D-
Truth latch
table

Edges Trigger Flip-Flops

The problem with the latch is that it responds to a change during a positive level (or a
negative level) of a clock pulse but in a sequential circuit we need to trigger the element
only at a signal transition instant.
Future university Digital system II lecture Notes

Flip flops are an application of logic gates. Flip-flops are the basic idea of a Random Access
Memory [RAM]. When a certain input value is given to them, they will be remembered and
executed, if the logic gates are designed correctly.
A higher application of flip flops is helpful in designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of a feedback circuit.
There are mainly four types of flip flops that are used in electronic circuits. They are:
The basic Flip Flop or S-R Flip Flop
Delay Flip Flop [D Flip Flop]
J-K Flip Flop T
Flip Flop
S-R Flip
Flop
The (Set-Reset) Flip-Flop can be designed with the help of two NOR gates and also two
NAND gates. The design of such a flip flop includes two inputs, called the SET [S] and RESET
[R]. There are also two outputs, Q and Q‘.

Logic
symbol

Logic Circuit
diagram
Future Digital system II lecture Notes
university
Truth
table
S R Q Q status
0 0 1 0 No Change
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 invalid

From the diagram the flip flop has mainly four states. They are:
S = 1, R = 0, Q = 1, Q = 0

This state is also called the SET

state. S = 0, R = 1, Q = 0, Q = 1
This state is known as the RESET
state.
In both the states you can see that the outputs are just compliments of each other and that
the value of Q follows the value of S.
S = 0, R = 0, Q & Q = Remember.
If both the values of S and R; are switched to 0, then the circuit remembers the value of S
and R in their previous state.
S=1, R=1—Q=0, Q‘=0 [Invalid]
This is an invalid state because the values of both Q and Q are 0.
They are supposed to be compliments of each other. Normally, this state must be avoided.
Clocked S-R Flip Flop

It is also called a Gated S-R flip flop. The problems with S-R flip flops using NOR and
NAND gate is the invalid state.
This problem can be overcome by using a bistable SR flip-flop that can change outputs
when certain invalid states are met, regardless of the condition of either the Set or the Reset
inputs.
For this, a clocked S-R flip flop is designed by adding two AND gates or a basic NOR Gate
flip flop. The circuit diagram and truth table is shown below.
Future Digital system II lecture Notes
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Logic circuit
diagram
Truth
table

A clock pulse is applied to the inputs of the AND Gate. When the value of the clock pulse is
‗0‘, the outputs of both the AND Gates remain ‗0‘. When a pulse is given the value of ‗1‘.
The values at S and R to pass through the NOR Gate flip flop. But when the values of both
S and R values turn ‗1‘, the HIGH value of CP causes both of them to turn to ‗0‘ for a short
moment. The pulse is removed; the flip flop state becomes intermediate. Thus either of the
two states may be caused, and it depends on whether the set or reset input of the flip-flop
remains a ‗1‘ longer than the transition to ‗0‘ at the end of the pulse.
Thus the invalid states can be eliminated.
D - Flip Flop
The D flip-flop tracks the input, making transitions with match those of the input D.
The D stands for "data"; this flip-flop stores the value that is on the data line. It can be
thought of as a basic memory cell.
D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an
inverter.
Future Digital system II lecture Notes
university

Logic
symbol

Logic circuit
diagram
Truth
table