5 4 3 2 1

D D

C C

B B

A A

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

5 4 3 2 1
 A B C D E

LCFC Confidential 1

HS45A/HS55A(NMD461) MB Schematics Document

TGL UP3 with DDR4
2020-04
2 2

REV:0.1

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential

NV N16x/N17x
Package: FCBGA595 Memory Bus DDR4 SO-DIMM+MDx4
1
PCI-Express 1.2V DDR4 Page 17/18 1

4x Gen3
VRAM: 256*32
GDDR5*2: 2GB x1

USB3.0 USB3.0 Conn

HDMI (DDI 1) x1
HDMI Conn.

x1
eDP x2
eDP Conn x1 USB3.0 Conn

Intel MCP
x1
SATA x1 USB2.0 Conn
SATA HDD
Tiger Lake-UP3 USB2.0
2 2

NGFF PCI-Express Finger print

SSD 4x Gen3
BGA1499
NGFF PCIe x1 45.5mm*25mm
USB2.0 x1
WLAN&BT

SPI SPI ROM (16MB+8MB)

W25Q128JVSIQ+W25R64JVSSIQ RPMC/
W25Q128JVSIQ+W25Q64JVSSIQ NON RPMC
SPK Conn. Page 07
Page 30
HD Audio x1
Realtek
HP&Mic RTS5199
3 Combo Conn. USB2.0 x1 3

Page 30 Page 43

I2C Touch Pad

Page 45
Page 3~16

SD Conn. LPC

IO Board EC GPIO
ITE IT8227E-LQFP128 HALL Sensor
Page 44

Int.KBD
Page 45
Thermal Sensor
F75303M Page 39

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 2 of 60
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
+3VALW S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

+5VALW +1.2V S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
+5VS
1 1
+3VS
V9B+ +3VALW_PCH +2.5V_DDR S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.8VALW +VCCST +CPU_CORE
+0.6VS
VCC_AUX +VCCSTG
State
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn @ Un-stuff
2 USB3.0 Conn 14@ For 14" part
3 NC 15@ For 15" part
USB3.0 4 NC
S0 O O O O 5
6
1 USB3.0 Conn
S3 O O O X 2 USB3.0 Conn
3 NC CD@ For cost down
4
S3 NC
2
Battery only O O O X USB2.0 5 Camere EMC@ For EMC part 2

6 Touch Screen EMC_15@ For EMC 15" part

7
S5 S4 Finger Print EMC_NS@ For EMC un-stuff part
AC Only O O X X 8 Card Reader
9 USB2.0 conn
10
S5 S4 Bluetooth
Battery only O X X X 5~8 DGPU
X4
S5 S4 9 WLAN
ME@ For ME part
AC & Battery X X X X PCIE 10 NC
don't exist
11 SATA HDD UMA@ For UMA part
12 NC OPT@ For NV GPU part
SMBUS Control Table 13~16 OPTN16@ For NV N16S-GTR GPU part
PCIE/SATA SSD
X4 OPTN17@ For NV N17S-G1 GPU part
SOURCE BATT Charger DGPU IT8227E Memory PCH PMIC SODIMM Thermal WLAN
Down Sensor WiMAX

3 3
EC_SMB_CK1 IT8227E
V V X V X X X X X X
EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK0 IT8227E
X X V V X X X X V X
EC_SMB_DA0 +3VS +3VG_AON +3VS TS@ For touch screen part
TP@ For TOuch Pad Part
EC_SMB_CK3 IT8227E
X X X V X X V X X X
EC_SMB_DA3 +3VAWL

PCH_SMB_CLK PCH
X X X X X V X V X X
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A 0.1

Date: Monday, November 02, 2020 Sheet 3 of 60

A B C D E
 5 4 3 2 1

UC1A

1 OF 21

AC2 AY2
DDIA_TXP_3 TCP0_TXRX_P1
AC1 AY1
DDIA_TXN_3 TCP0_TXRX_N1
AD2 BB1
DDIA_TXP_2 TCP0_TXRX_P0
AD1 BB2
CPU_EDP_TX1+ DDIA_TXN_2 TCP0_TXRX_N0
33 CPU_EDP_TX1+ AF1 AM5
CPU_EDP_TX1- DDIA_TXP_1 TCP0_TX_P1
33 CPU_EDP_TX1- AF2 AM7
CPU_EDP_TX0+ DDIA_TXN_1 TCP0_TX_N1
33 CPU_EDP_TX0+ AG2 AT7
CPU_EDP_TX0- DDIA_TXP_0 TCP0_TX_P0
33 CPU_EDP_TX0- AG1 AT5
DDIA_TXN_0 TCP0_TX_N0
AP7
CPU_EDP_AUX TCP0_AUX_P
AJ2 AP5
33 CPU_EDP_AUX CPU_EDP_AUX# DDIA_AUX_P TCP0_AUX
33 CPU_EDP_AUX# AJ1
DDIA_AUX
AT2
TCP1_TXRX_P1
DN4 AT1
D GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 D
DT6 AU1
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0
AU2
CPU_EDP_HPD TCP1_TXRX_N0
33 CPU_EDP_HPD DR5 AD5
GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1
AD7
CPU_HDMI_CLKP TCP1_TX_N1
34 CPU_HDMI_CLKP T12 AH7
CPU_HDMI_CLKN DDIB_TXP_3 TCP1_TX_P0
HDMI CLK 34 CPU_HDMI_CLKN CPU_HDMI_TXP0
T11
DDIB_TXN_3 TCP1_TX_N0
AH5
34 CPU_HDMI_TXP0 Y11 AF7
CPU_HDMI_TXN0 DDIB_TXP_2 TCP1_AUX_P
HDMI D0 34 CPU_HDMI_TXN0 CPU_HDMI_TXP1
Y9
DDIB_TXN_2 TCP1_AUX
AF5
34 CPU_HDMI_TXP1 T9
CPU_HDMI_TXN1 DDIB_TXP_1
HDMI D1 34 CPU_HDMI_TXN1 CPU_HDMI_TXP2
P9
DDIB_TXN_1 TCP2_TXRX_P1
BF1
34 CPU_HDMI_TXP2 V11 BF2
CPU_HDMI_TXN2 DDIB_TXP_0 TCP2_TXRX_N1
HDMI D2 34 CPU_HDMI_TXN2 V9
DDIB_TXN_0 TCP2_TXRX_P0
BE2
BE1
TCP2_TXRX_N0
AB9 BD7
DDIB_AUX_P TCP2_TX_P1
AD9 BD5
DDIB_AUX TCP2_TX_N1
AY5
PCH_HDMI_DDC_CLK TCP2_TX_P0
34 PCH_HDMI_DDC_CLK DM29 AY7
PCH_HDMI_DDC_DATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
DK27 BB5
34 PCH_HDMI_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P
BB7
CPU_HDMI_HPD TCP2_AUX
34 CPU_HDMI_HPD DG43
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
BK1
TCP3_TXRX_P1
DG47 BK2
GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
BJ1
TCP3_TXRX_N0
DU8 BM7
GPP_E19 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1
DV8 BM5
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1
BH5
TCP3_TX_P0
DF6 BH7
GPP_E21 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0
DD6 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P
BK7
TCP3_AUX
DN23
GPP_D10 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# TCRCOMP_P
DM23 AN2
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P TCRCOMP_N RC401 1 2
AN1
TC_RCOMP 1/20W_150_1%_0201
DK23
GPP_D12 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO DSI_DE_TE_2 1
DN21 M8
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2 @ TP401
DF43 AB1 EDP_COMP
GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
C DF45 C
GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
DF47 CE4 DISP_UTILS
1
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1

1/20W_150_1%_0201
1
@
USB_OC1# DH52

2 RC402
41 USB_OC1# USB_OC2# GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
DK45 TP402
42 USB_OC2# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
+3VS PCH_ENVDD DM8
33 PCH_ENVDD EDP_VDDEN
PCH_ENBKL DN8
33,44 PCH_ENBKL EDP_BKLTEN
PCH_EDP_PWM DG10
33 PCH_EDP_PWM EDP_BKLTCTL
RPC401
1 4 PCH_HDMI_DDC_CLK
2 3 PCH_HDMI_DDC_DATA
TGLLAKE-U_BGA1449
2.2K_0404_4P2R_5% @

+3VALW_PCH

1/20W_4.7K_1%_0201 2 @ 1 RC403 GPP_E19

1/20W_20K_5%_0201 2 @ 1 RC404

1/20W_4.7K_5%_0201 2 @ 1 RC405 GPP_E21

1/20W_20K_5%_0201 2 @ 1 RC406

1/20W_4.7K_5%_0201 2 @ 1 RC407 GPP_D10

1/20W_20K_5%_0201 2 @ 1 RC408

1/20W_4.7K_5%_0201 2 @ 1 RC409 GPP_D12

1/20W_20K_5%_0201 2 @ 1 RC410
B B
An external pull-up resistor is required if the pin is
used as HDMI Display I2C, instead of TBT LSx
0 = DDPx I2C / TBT LSx pins at 1.8V
1 = DDPx I2C / TBT LSx pins at 3.3V

+1.8VALW_PCH
GPIO Group Power Supply

RC411 1 2 10K_0201_5% USB_OC1#

GPP_A 1.8V
RC412 1 2 10K_0201_5% USB_OC2#
GPP_B/C/D/E 3.3V

RC413 1 2 100K_0201_5%CPU_EDP_HPD
GPP_F 1.8V(only)

GPP_G/H 3.3V
CC401
2 1 GPP_R/S 1.8V
0.33U 10V K X5R 0402
@ GPD 3.3V(only)
RPC402
4 1 PCH_ENVDD
3 2 PCH_ENBKL

100K_0404_4P2R_5%

CC402
2 1
A A
0.33U 10V K X5R 0402
@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 DDI/EDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

DDRA_DQS#[0..7] DDRB_CLK0#
18 DDRA_DQS#[0..7]
DDRA_DQS[0..7]
18 DDRA_DQS[0..7] 1
DDRB_DQS#[0..7] CC502
17 DDRB_DQS#[0..7] 3.3P_50V_C_NPO_0201
DDRB_DQS[0..7] 2
17 DDRB_DQS[0..7] DDRB_CLK0 @
SO_DIMM
UC1B
UC1C
MD
2 OF 21
17 DDRB_DQ[0..63] 3 OF 21
DDR4 (NIL)/LP4 DDR4/LP4
18 DDRA_DQ[0..63] DDRA_DQ7 CP53 DDRA_CLK1 DDR4/LP4
BT42 DDRA_CLK1 18
DDR4 (NIL)/LP4
D DDRA_DQ6 CP52 DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P DDRA_CLK1# DDRB_DQ7 D
BT41 DDRA_CLK1# 18 AL53 R41
DDRA_DQ5 CP50 DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK DDRB_DQ6 DDR1_DQ0_7/DDR4_DQ0_7 DDR1_CLK_P1/DDR7_CLK_P
BP52 AL52 R42
DDRA_DQ4 CP49 DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P DDRB_DQ5 DDR1_DQ0_6/DDR4_DQ0_6 DDR1_CLK_N1/DDR7_CLK
BP53 AL50 M52
DDRA_DQ3 CU53 DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK DDRB_DQ4 DDR1_DQ0_5/DDR4_DQ0_5 NC/DDR6_CLK_P
CD42 AL49 M53
DDRA_DQ2 CU52 DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P DDRB_DQ3 DDR1_DQ0_4/DDR4_DQ0_4 NC/DDR6_CLK
CD41 AP53 AC42
DDRA_DQ1 CU50 DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK DDRA_CLK0 DDRB_DQ2 DDR1_DQ0_3/DDR4_DQ0_3 NC/DDR5_CLK_P
CC52 DDRA_CLK0 18 AP52 AC41
DDRA_DQ0 CU49 DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P DDRA_CLK0# DDRB_DQ1 DDR1_DQ0_2/DDR4_DQ0_2 NC/DDR5_CLK DDRB_CLK0
CC53 DDRA_CLK0# 18 AP50 Y52 DDRB_CLK0 17
DDRA_DQ15 CH53 DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK DDRB_DQ0 DDR1_DQ0_1/DDR4_DQ0_1 DDR1_CLK_P0/DDR4_CLK_P DDRB_CLK0#
AP49 Y53 DDRB_CLK0# 17
DDRA_DQ14 CH52 DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4 DDRB_DQ15 DDR1_DQ0_0/DDR4_DQ0_0 DDR1_CLK_N0/DDR4_CLK
BT45 AF53
DDRA_DQ13 CH50 DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0 DDRB_DQ14 DDR1_DQ1_7/DDR4_DQ1_7 DDR4/LP4
BT47 AF52 R47
DDRA_DQ12 CH49 DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1 DDRB_DQ13 DDR1_DQ1_6/DDR4_DQ1_6 NC/DDR7_CKE0
BN51 AF50 R45
DDRA_DQ11 CL53 DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0 DDRB_DQ12 DDR1_DQ1_5/DDR4_DQ1_5 NC/DDR7_CKE1
BN53 AF49 K51
DDRA_DQ10 CL52 DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1 DDRB_DQ11 DDR1_DQ1_4/DDR4_DQ1_4 NC/DDR6_CKE0
CD45 AH53 K53
DDRA_DQ9 CL50 DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0 DDRB_DQ10 DDR1_DQ1_3/DDR4_DQ1_3 NC/DDR6_CKE1
CD47 AH52 AC47
DDRA_DQ8 CL49 DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1 DDRB_DQ9 DDR1_DQ1_2/DDR4_DQ1_2 NC/DDR5_CKE0
CA51 AH50 AC45
DDRA_DQ23 CT47 DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0 DDRB_DQ8 DDR1_DQ1_1/DDR4_DQ1_1 NC/DDR5_CKE1
CA53 AH49 W51
DDRA_DQ22 CV47 DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1 DDRB_DQ23 DDR1_DQ1_0/DDR4_DQ1_0 NC/DDR4_CKE0
AR41 W53
DDRA_DQ21 CT45 DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4 DDRA_CKE1 DDRB_DQ22 DDR1_DQ2_7/DDR5_DQ0_7 NC/DDR4_CKE1
BU52 DDRA_CKE1 18 AV42 DDR4/LP4
DDRA_DQ20 CV45 DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4 DDRA_CKE0 DDRB_DQ21 DDR1_DQ2_6/DDR5_DQ0_6
BL50 DDRA_CKE0 18 AR42 P52
DDRA_DQ19 CT42 DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5 DDRB_DQ20 DDR1_DQ2_5/DDR5_DQ0_5 DDR1_CKE1/DDR6_CA4 DDRB_CKE0
AV41 J50 DDRB_CKE0 17
DDRA_DQ18 CV42 DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4 DDRA_CS1# DDRB_DQ19 DDR1_DQ2_4/DDR5_DQ0_4 DDR1_CKE0/DDR6_CA5
CF42 DDRA_CS1# 18 AR45
DDRA_DQ17 CT41 DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1 DDRA_CS0# DDRB_DQ18 DDR1_DQ2_3/DDR5_DQ0_3 DDR4/LP4
CF47 DDRA_CS0# 18 AV45 AE42
DDRA_DQ16 CV41 DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC DDRB_DQ17 DDR1_DQ2_2/DDR5_DQ0_2 DDR1_CS1/DDR5_CA1 DDRB_CS0#
AR47 AE47 DDRB_CS0# 17
DDRA_DQ31 CK47 DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4 DDRB_DQ16 DDR1_DQ2_1/DDR5_DQ0_1 DDR1_CS0/NC
CE53 AV47
DDRA_DQ30 CM47 DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0 DDRB_DQ31 DDR1_DQ2_0/DDR5_DQ0_0 DDR4/LP4
CE50 AJ41 N42
DDRA_DQ29 CK45 DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1 DDRB_DQ30 DDR1_DQ3_7/DDR5_DQ1_7 NC/DDR7_CA5
BL53 AJ42 N45
DDRA_DQ28 CM45 DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0 DDRB_DQ29 DDR1_DQ3_6/DDR5_DQ1_6 NC/DDR7_CA4
BP47 AL41 N44
DDRA_DQ27 CK42 DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5 DDRB_DQ28 DDR1_DQ3_5/DDR5_DQ1_5 NC/DDR7_CA3
BP42 AL42 N47
DDRA_DQ26 CM42 DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4 DDRB_DQ27 DDR1_DQ3_4/DDR5_DQ1_4 NC/DDR7_CA2
BP45 AJ45 J53
DDRA_DQ25 CM41 DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3 DDRB_DQ26 DDR1_DQ3_3/DDR5_DQ1_3 NC/DDR6_CS0
BP44 AJ47 AC50
DDRA_DQ24 CK41 DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2 DDRB_DQ25 DDR1_DQ3_2/DDR5_DQ1_2 NC/DDR4_CA1
AL45 AC53
DDRA_DQ39 BF53 DDR0_DQ3_0/DDR1_DQ1_0 DDR4 (NIL)/LP4 DDRA_DQS7 DDRB_DQ24 DDR1_DQ3_1/DDR5_DQ1_1 NC/DDR4_CA0
BB44 AL47
DDRA_DQ38 BF52 DDR0_DQ4_7/DDR2_DQ0_7 DDR0_DQSP_7/DDR3_DQSP_1 DDRA_DQS#7 DDRB_DQ39 DDR1_DQ3_0/DDR5_DQ1_0 DDR4 (NIL)/LP4 DDRB_DQS7
BD44 A43 K36
DDRA_DQ37 BF50 DDR0_DQ4_6/DDR2_DQ0_6 DDR0_DQSN_7/DDR3_DQSN_1 DDRA_DQS6 DDRB_DQ38 DDR1_DQ4_7/DDR6_DQ0_7 DDR1_DQSP_7/DDR7_DQSP_1 DDRB_DQS#7
BK44 B43 K38
DDRA_DQ36 BF49 DDR0_DQ4_5/DDR2_DQ0_5 DDR0_DQSP_6/DDR3_DQSP_0 DDRA_DQS#6 DDRB_DQ37 DDR1_DQ4_6/DDR6_DQ0_6 DDR1_DQSN_7/DDR7_DQSN_1 DDRB_DQS6
BH44 D43 G44
DDRA_DQ35 BH53 DDR0_DQ4_4/DDR2_DQ0_4 DDR0_DQSN_6/DDR3_DQSN_0 DDRA_DQS5 DDRB_DQ36 DDR1_DQ4_5/DDR6_DQ0_5 DDR1_DQSP_6/DDR7_DQSP_0 DDRB_DQS#6
BA51 E44 J44
DDRA_DQ34 BH52 DDR0_DQ4_3/DDR2_DQ0_3 DDR0_DQSP_5/DDR2_DQSP_1 DDRA_DQS#5 DDRB_DQ35 DDR1_DQ4_4/DDR6_DQ0_4 DDR1_DQSN_6/DDR7_DQSN_0 DDRB_DQS5
BA50 A46 D39
DDRA_DQ33 BH50 DDR0_DQ4_2/DDR2_DQ0_2 DDR0_DQSN_5/DDR2_DQSN_1 DDRA_DQS4 DDRB_DQ34 DDR1_DQ4_3/DDR6_DQ0_3 DDR1_DQSP_5/DDR6_DQSP_1 DDRB_DQS#5
C BG51 B46 C39 C
DDRA_DQ32 BH49 DDR0_DQ4_1/DDR2_DQ0_1 DDR0_DQSP_4/DDR2_DQSP_0 DDRA_DQS#4 DDRB_DQ33 DDR1_DQ4_2/DDR6_DQ0_2 DDR1_DQSN_5/DDR6_DQSN_1 DDRB_DQS4
BG50 D46 C45
DDRA_DQ47 AY53 DDR0_DQ4_0/DDR2_DQ0_0 DDR0_DQSN_4/DDR2_DQSN_0 DDRA_DQS3 DDRB_DQ32 DDR1_DQ4_1/DDR6_DQ0_1 DDR1_DQSP_4/DDR6_DQSP_0 DDRB_DQS#4
CK44 E47 D45
DDRA_DQ46 AY52 DDR0_DQ5_7/DDR2_DQ1_7 DDR0_DQSP_3/DDR1_DQSP_1 DDRA_DQS#3 DDRB_DQ47 DDR1_DQ4_0/DDR6_DQ0_0 DDR1_DQSN_4/DDR6_DQSN_0 DDRB_DQS3
CM44 E38 AJ44
DDRA_DQ45 AY50 DDR0_DQ5_6/DDR2_DQ1_6 DDR0_DQSN_3/DDR1_DQSN_1 DDRA_DQS2 DDRB_DQ46 DDR1_DQ5_7/DDR6_DQ1_7 DDR1_DQSP_3/DDR5_DQSP_1 DDRB_DQS#3
CT44 D38 AL44
DDRA_DQ44 AY49 DDR0_DQ5_5/DDR2_DQ1_5 DDR0_DQSP_2/DDR1_DQSP_0 DDRA_DQS#2 DDRB_DQ45 DDR1_DQ5_6/DDR6_DQ1_6 DDR1_DQSN_3/DDR5_DQSN_1 DDRB_DQS2
CV44 B38 AV44
DDRA_DQ43 BC53 DDR0_DQ5_4/DDR2_DQ1_4 DDR0_DQSN_2/DDR1_DQSN_0 DDRA_DQS1 DDRB_DQ44 DDR1_DQ5_5/DDR6_DQ1_5 DDR1_DQSP_2/DDR5_DQSP_0 DDRB_DQS#2
CK51 A38 AR44
DDRA_DQ42 BC52 DDR0_DQ5_3/DDR2_DQ1_3 DDR0_DQSP_1/DDR0_DQSP_1 DDRA_DQS#1 DDRB_DQ43 DDR1_DQ5_4/DDR6_DQ1_4 DDR1_DQSN_2/DDR5_DQSN_0 DDRB_DQS1
CK50 E41 AG51
DDRA_DQ41 BC50 DDR0_DQ5_2/DDR2_DQ1_2 DDR0_DQSN_1/DDR0_DQSN_1 DDRA_DQS0 DDRB_DQ42 DDR1_DQ5_3/DDR6_DQ1_3 DDR1_DQSP_1/DDR4_DQSP_1 DDRB_DQS#1
CR51 D40 AG50
DDRA_DQ40 BC49 DDR0_DQ5_1/DDR2_DQ1_1 DDR0_DQSP_0/DDR0_DQSP_0 DDRA_DQS#0 DDRB_DQ41 DDR1_DQ5_2/DDR6_DQ1_2 DDR1_DQSN_1/DDR4_DQSN_1 DDRB_DQS0
CR50 B40 AN51
DDRA_DQ55 BK47 DDR0_DQ5_0/DDR2_DQ1_0 DDR0_DQSN_0/DDR0_DQSN_0 DDRB_DQ40 DDR1_DQ5_1/DDR6_DQ1_1 DDR1_DQSP_0/DDR4_DQSP_0 DDRB_DQS#0
DDR4/LP4 A40 AN50
DDRA_DQ54 BK45 DDR0_DQ6_7/DDR3_DQ0_7 DDRA_ODT1 DDRB_DQ55 DDR1_DQ5_0/DDR6_DQ1_0 DDR1_DQSN_0/DDR4_DQSN_0
CF44 DDRA_ODT1 18 G42
DDRA_DQ53 BH47 DDR0_DQ6_6/DDR3_DQ0_6 DDR0_ODT1/DDR1_CA0 DDRA_ODT0 DDRB_DQ54 DDR1_DQ6_7/DDR7_DQ0_7 DDR4/LP4
CF45 DDRA_ODT0 18 G41 AE44
DDRA_DQ52 BH45 DDR0_DQ6_5/DDR3_DQ0_5 DDR0_ODT0/DDR1_CS0 DDRB_DQ53 DDR1_DQ6_6/DDR7_DQ0_6 DDR1_ODT1/DDR5_CA0 DDRB_ODT0
DDR4/LP4 J41 AE45 DDRB_ODT0 17
DDRA_DQ51 BH42 DDR0_DQ6_4/DDR3_DQ0_4 DDRA_MA16_RAS# DDRB_DQ52 DDR1_DQ6_5/DDR7_DQ0_5 DDR1_ODT0/DDR5_CS0
CB47 DDRA_MA16_RAS# 18 J42
DDRA_DQ50 BK42 DDR0_DQ6_3/DDR3_DQ0_3 DDR0_MA16/DDR1_CA4 DDRA_MA15_CAS# DDRB_DQ51 DDR1_DQ6_4/DDR7_DQ0_4 DDR4/LP4 DDRB_MA16_RAS#
CB44 DDRA_MA15_CAS# 18 G45 AA47 DDRB_MA16_RAS# 17
DDRA_DQ49 BK41 DDR0_DQ6_2/DDR3_DQ0_2 DDR0_MA15/DDR1_CA3 DDRA_MA14_WE# DDRB_DQ50 DDR1_DQ6_3/DDR7_DQ0_3 DDR1_MA16/DDR5_CA4 DDRB_MA15_CAS#
CB45 DDRA_MA14_WE# 18 J45 AA44 DDRB_MA15_CAS# 17
DDRA_DQ48 BH41 DDR0_DQ6_1/DDR3_DQ0_1 DDR0_MA14/DDR1_CA2 DDRA_MA13 DDRB_DQ49 DDR1_DQ6_2/DDR7_DQ0_2 DDR1_MA15/DDR5_CA3 DDRB_MA14_WE#
CF41 DDRA_MA13 18 G47 AA45 DDRB_MA14_WE# 17
DDRA_DQ63 BD47 DDR0_DQ6_0/DDR3_DQ0_0 DDR0_MA13/DDR1_CS1 DDRA_MA12 DDRB_DQ48 DDR1_DQ6_1/DDR7_DQ0_1 DDR1_MA14/DDR5_CA2 DDRB_MA13
BU53 DDRA_MA12 18 J47 AE41 DDRB_MA13 17
DDRA_DQ62 BB47 DDR0_DQ7_7/DDR3_DQ1_7 DDR0_MA12/DDR2_CA1 DDRA_MA11 DDRB_DQ63 DDR1_DQ6_0/DDR7_DQ0_0 DDR1_MA13/DDR5_CS1 DDRB_MA12
BT51 DDRA_MA11 18 G38 P53 DDRB_MA12 17
DDRA_DQ61 BD45 DDR0_DQ7_6/DDR3_DQ1_6 DDR0_MA11/NC DDRA_MA10 DDRB_DQ62 DDR1_DQ7_7/DDR7_DQ1_7 DDR1_MA12/DDR6_CA1 DDRB_MA11
BV42 DDRA_MA10 18 G36 N51 DDRB_MA11 17
DDRA_DQ60 BB45 DDR0_DQ7_5/DDR3_DQ1_5 DDR0_MA10/DDR3_CA1 DDRA_MA9 DDRB_DQ61 DDR1_DQ7_6/DDR7_DQ1_6 DDR1_MA11/NC DDRB_MA10
BU50 DDRA_MA9 18 H36 U42 DDRB_MA10 17
DDRA_DQ59 BB42 DDR0_DQ7_4/DDR3_DQ1_4 DDR0_MA9/DDR2_CA0 DDRA_MA8 DDRB_DQ60 DDR1_DQ7_5/DDR7_DQ1_5 DDR1_MA10/DDR7_CA1 DDRB_MA9
BY53 DDRA_MA8 18 H38 P50 DDRB_MA9 17
DDRA_DQ58 BB41 DDR0_DQ7_3/DDR3_DQ1_3 DDR0_MA8/DDR0_CA2 DDRA_MA7 DDRB_DQ59 DDR1_DQ7_4/DDR7_DQ1_4 DDR1_MA9/DDR6_CA0 DDRB_MA8
CA50 DDRA_MA7 18 N36 U53 DDRB_MA8 17
DDRA_DQ57 BD42 DDR0_DQ7_2/DDR3_DQ1_2 DDR0_MA7/DDR0_CA4 DDRA_MA6 DDRB_DQ58 DDR1_DQ7_3/DDR7_DQ1_3 DDR1_MA8/DDR4_CA2 DDRB_MA7
BY52 DDRA_MA6 18 L36 W50 DDRB_MA7 17
DDRA_DQ56 BD41 DDR0_DQ7_1/DDR3_DQ1_1 DDR0_MA6/DDR0_CA3 DDRA_MA5 DDRB_DQ57 DDR1_DQ7_2/DDR7_DQ1_2 DDR1_MA7/DDR4_CA4 DDRB_MA6
BY50 DDRA_MA5 18 L38 U52 DDRB_MA6 17
DDR0_DQ7_0/DDR3_DQ1_0 DDR0_MA5/DDR0_CA5 DDRA_MA4 DDRB_DQ56 DDR1_DQ7_1/DDR7_DQ1_1 DDR1_MA6/DDR4_CA3 DDRB_MA5
CD51 DDRA_MA4 18 N38 U50 DDRB_MA5 17
DDR0_MA4/DDR0_CS0 DDRA_MA3 DDR1_DQ7_0/DDR7_DQ1_0 DDR1_MA5/DDR4_CA5 DDRB_MA4
CD53 DDRA_MA3 18 AA51 DDRB_MA4 17
DDR0_MA3/DDR0_CS1 DDRA_MA2 DDR1_MA4/DDR4_CS0 DDRB_MA3
BV47 DDRA_MA2 18 AA53 DDRB_MA3 17
DDR0_MA2/DDR3_CS0 DDRA_MA1 DDR1_MA3/DDR4_CS1 DDRB_MA2
CE52 DDRA_MA1 18 U47 DDRB_MA2 17
DDR0_MA1/NC DDRA_MA0 DDR1_MA2/DDR7_CS0 DDRB_MA1
BV41 DDRA_MA0 18 AC52 DDRB_MA1 17
DDR0_MA0/NC DDR1_MA1/NC DDRB_MA0
DDR4/LP4 U41 DDRB_MA0 17
DDRA_BG1 DDR1_MA0/NC
BN50 DDRA_BG1 18
DDR0_BG1/DDR2_CA2 DDRA_BG0 DDR4/LP4 DDRB_BG1
BL52 DDRA_BG0 18 K50 DDRB_BG1 17
DDR0_BG0/DDR2_CA3 DDR1_BG1/DDR6_CA2 DDRB_BG0
DDR4/LP4 J52 DDRB_BG0 17
DDRA_BS1# DDR1_BG0/DDR6_CA3
CB42 DDRA_BS1# 18
DDR0_BA1/DDR1_CA5 DDRA_BS0# DDR4/LP4 DDRB_BS1#
BV44 DDRA_BS0# 18 AA42 DDRB_BS1# 17
DDR0_BA0/DDR3_CA0 DDR1_BA1/DDR5_CA5 DDRB_BS0#
DDR4/LP4 U44 DDRB_BS0# 17
B DDRA_ACT# DDR1_BA0/DDR7_CA0 B
BT53 DDRA_ACT# 18
DDR0_ACT#/DDR2_CS1 DDRB_ACT#
N53 DDRB_ACT# 17
DDR4/LP4 DDRA_PAR DDR1_ACT#/DDR6_CS1
BV45 DDRA_PAR 18
DDR0_PAR/DDR3_CS1 DDRB_PAR
U45 DDRB_PAR 17
DDR4 DDRA_ALERT# DDR1_PAR/DDR7_CS1
AU50 DDRA_ALERT# 18
DDR0_ALERT# DDR_SA_VREFCA DDRB_ALERT#
AU49 DDR_SA_VREFCA 18 AU53 DDRB_ALERT# 17
DDR0_VREF_CA DDR1_ALERT# DDR_SB_VREFCA
AU52 DDR_SB_VREFCA 17
DDR_VTT_CNTL DDR1_VREF_CA
E52
DDR_VTT_CTL
DV47 CPU_DRAMRST#_R
DRAM_RESET#
C49DDR_RCOMP_0 1/20W_100_1%_0201 2 1RC501 @ TGLLAKE-U_BGA1449
DDR_RCOMP

@ TGLLAKE-U_BGA1449
+3VALW
+1.2V
1

1
RC505 RC504
1/16W_470_1%_0402 100K_0402_5%

RC507
2

2
CPU_DRAMRST#_R 1 2
CPU_DRAMRST# 17,18 CPU_DRAMPG_CNTL 55
0_0402_5% +1.2V
@ 1 1
CC501 RC506 C
0.1U_6.3V_K_X5R_0201 1 2 2 QC501
@ 1K_0402_5% B MMBT3904WH_SOT323-3
2 E
3

DDR_VTT_CNTL

A A
2

RC508
10K_0402_5%
@
1

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 DDR4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCSTG_TERM

RC601 1 2 51_0402_5% PCH_JTAG_TDO_CPU

RC602 1 @ 2 51_0402_5% PCH_JTAG_TDI_CPU

RC603 1 @ 2 51_0402_5% PCH_JTAG_TMS_CPU

RC604 1 2 1K_0402_5% H_PROCHOT#

RC605 1 2 51_0402_5% PCH_TCK_JTAGX_CPU

RC1613 1 2 51_0402_5% XDP_TRST_CPU_N

@ UC1U +VCCSTG_CPU
RC2020 1 2 51_0402_5% PCH_JTAG_TCK
21 OF 21
@
D D

1
CATERR# M7 K4 XDP_TRST_CPU_N 1 TP601 @
H_PECI CATERR# PROC_TRST# PCH_JTAG_TMS_CPU RC30
44 H_PECI BK9 B9
RC606 1 2 499_0402_1% H_PROCHOT#_R PECI PROC_TMS PCH_JTAG_TDO_CPU 1K_0201_5%
13,44,55 H_PROCHOT# E2 D12 EAR
H_THRMTRIP# PROCHOT# PROC_TDO PCH_JTAG_TDI_CPU
M5 A12
+3VALW_PCH THRMTRIP# PROC_TDI
B6 PCH_TCK_JTAGX_CPU Stall CPU reset sequence
PROC_TCK until de-asserted:

2
RC608 1 2 1/20W_49.9_1%_0201 PROC_OPI_RCOMP CT39
RC610 1 2 1/20W_49.9_1%_0201 PCH_OPI_RCOMP CB9
PROC_POPIRCOMP
D8 PCH_TCK_JTAGX_CPU - 1 = (Default) Normal CPU_EAR
PCH_OPIRCOMP PCH_JTAGX PCH_JTAG_TMS_CPU Operation; No stall.
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

CW12 A9
TP_1 PCH_TMS - 0 = Stall
1

CM39 E12 PCH_JTAG_TDO_CPU

GPP_H0: Boot Strap 1 TP_2 PCH_TDO

1
B12 PCH_JTAG_TDI_CPU
RC637

RC638

RC639

GPP_H1: Boot Strap 2 DBG_PMODE DF4

PCH_TDI
A7 PCH_JTAG_TCK 1 TP602 @ RC34
GPP_H2: Boot Strap 3 DBG_PMODE PCH_TCK
H4 XDP_TRST_CPU_N @ 1K_0201_5%
@ @ @ Boot Strap, Rising edge of RSMRST# DB42
PCH_TRST#
These straps has a 20 kohm ± 30% internal pull-down. GPP_B4/CPU_GP3
2

DB41 C11 PROC_PREQ_N 1 TP604 @

They are bit [3:1] of a total of 4-bit encoded pin straps GPP_B3/CPU_GP2 PROC_PREQ#

2
GPP_H0 DF8 D11 PROC_PRDY_N 1 TP603 @
GPP_H1 for boot configuration. GPP_E7/CPU_GP1 PROC_PRDY#
44 EC_SCI# DU5
GPP_H2 GPP_E3/CPU_GP0 CPU_EAR
Refer to Boot Strap 0 (on GPP_C5) for the encoding. G1
GPP_H2 EAR_N/EAR_N_TEST_NCTF
Notes: 1. The internal pull-down is disabled after DF31
GPP_H2
1/20W_20K_5%_0201

1/20W_20K_5%_0201
1/20W_20K_5%_0201

RSMRST# de-asserts. GPP_H1 DV32 DT15 GPP_F7

GPP_H1 GPP_F7
1

GPP_H0
2. This signal is in the primary well. DW32 DR15
RC640

GPP_H0 GPP_F9 GPP_F10

DT14
RC641

RC642

GPP_F10
DJ27
GPP_H19/TIME_SYNC0 GPP_F7 RC50 1 @ 2 1/20W_20K_5%_0201
@ @ @
2

@ TGLLAKE-U_BGA1449 GPP_F10 RC49 1 @ 2 1/20W_20K_5%_0201

GPP_F7 and GPP_F10:

0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled Reserved, Rising edge of RSMRST#
0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled This strap has a 20 kohm ± 30% internal pull-down.
0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI This strap should sample LOW. There should NOT be any onboard
1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device). device driving it to opposite direction during strap sampling.
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well.

C C

+VCCST_CPU

RC615 1 2 1K_0402_5% H_THRMTRIP#

RC616 1 2 1K_0402_5% CATERR#

+3VS

RC617 1 2 10K_0402_5% EC_SCI#

UC1G
7 OF 21

RC618 1 2 1/20W_33_1%_0201 HDA_BCLK_R DR38 DW15

30 HDA_BITCLK_AUDIO GPP_R0/HDA_BCLK/I2S0_SCLK GPP_F8/I2S_MCLK2_INOUT
RC619 1 2 1/20W_33_1%_0201 HDA_SYNC_R DU37 DW24
30 HDA_SYNC_AUDIO GPP_R1/HDA_SYNC/I2S0_SFRM GPP_D19/I2S_MCLK1
RC620 1 2 1/20W_33_1%_0201 HDA_SDO_R DT37
30 HDA_SDOUT_AUDIO HDA_SDIN0 GPP_R2/HDA_SDO/I2S0_TXD
30 HDA_SDIN0 DV37 DG41
GPP_R3/HDA_SDI0/I2S0_RXD GPP_A23/I2S1_SCLK
DT38
GPP_R7/I2S1_SFRM
DV41 DV38
GPP_R4/HDA_RST# GPP_R6/I2S1_TXD
DL53 DW38
RC624 1 2 33_0402_5% CNVI_RF_RESET#_PCH GPP_A7/I2S2_SCLK/DMIC_CLK_A0 GPP_R5/HDA_SDI1/I2S1_RXD
40 CNVI_RF_RESET# DG51
GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0
DG50 DN31 PCH_DMIC_CLK0 [30]
GPP_A10/I2S2_RXD/DMIC_DATA1 GPP_S6/SNDW3_CLK/DMIC_CLK_A0
DM31 PCH_DMIC_DAT0 [30]
RC626 1 2 33_0402_5% CNVI_MODEM_CLKREQ_PCH GPP_S7/SNDW3_DATA/DMIC_DATA0
40 CNVI_MODEM_CLKREQ DL49
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1
DL52 DK33
RC861 GPP_A11/PMC_I2C_SDA/I2S3_SCLK GPP_S4/SNDW2_CLK/DMIC_CLK_A1
@ DK31
1 2 0_0201_5% GPP_S5/SNDW2_DATA/DMIC_DATA1
[40] PCH_BT_OFF# DH49
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
DW35
1/20W_200_1%_0201 2 1 RC627 SNDW_RCOMP DF33 GPP_S2/SNDW1_CLK/DMIC_CLK_B0
DV35
SNDW_RCOMP GPP_S3/SNDW1_DATA/DMIC_CLK_B1
DT32
GPP_S0/SNDW0_CLK
DR35
B GPP_S1/SNDW0_DATA B

PCH_DMIC_CLK0
@ TGLLAKE-U_BGA1449

68P_0402_50V8J 2 1 CC601 HDA_BCLK_R

@ 2P_25V_C_NPO_0201 2 1 CC602 HDA_SYNC_R

EMC_NS@
2
@ 2P_25V_C_NPO_0201 2 1 CC603 HDA_SDO_R
CC1449
@ 10P_0201_50V8F 2 1 CC605 HDA_SDIN0 100P_0402_50V8J
1
EMC request for reserve 0821
75K_0402_1% 2 1 RC631 CNVI_RF_RESET#_PCH UC1D
4 OF 21
EMC_NS@ 33P_0201_50V8-J 2 1 CC604 CNVI_MODEM_CLKREQ_PCH

DV24
RSVD_2
DW47
RSVD_3
DW49
RSVD_4
A48
RSVD_5
+1.8VALW_PCH
@ TGLLAKE-U_BGA1449
1

RC622
4.7K_0402_5%
+VCC1.05_OUT_FET @
2

@ HDA_SDO_R 0_0402_5% 2 1 RC625

DBG_PMODE ME_FLASH 44
RC632 1 2 1K_0201_5%
GPP_R2(HDA_SDO_R):
A RC633 1 @ 2 1K_0201_5% This signal has a 20K ±30% internal pull-down. A
0 = Enable security measures defined in the Flash Descriptor. (Default)
1 = Disable Flash Descriptor Security (override). This strap should only
DBG_PMODE(Reserved): Rising edge of RSMRST# be asserted high using external Pull-up in manufacturing/debug
This strap has a 20 kohm ± 30% internal pull-up. environments ONLY.
This strap should sample high. There should NOT be Notes:
any on-board device driving it to opposite direction 1. The internal pull-down is disabled after PCH_PWROK is high.
during strap sampling. 2. This signal is in the primary well.
Notes:
1. The internal pull-up is disabled after RSMRST# deasserts.
2. This signal is in the primary well. Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 JTAG/AUDIO/SDIO/GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

RC814 1 @ 2 1/20W_150K_5%_0201 SML1_ALERT#

RC818 1 2 1/20W_20K_5%_0201

UC1E
5 OF 21
GPP_B23(SML1_ALERT#):
+3VALW_PCH RC734 This signal has a 20K+-30% internal pull-down.
SPI_CLK @ PCH_SPI_CLK PCH_SMB_CLK 0 = 38.4 MHz clock (direct from crystal) (default)
1 2 0_0201_5% DJ37 DK21
GPP_E6 [44] SPI_CLK SPI_IO3 @ PCH_SPI_IO3 SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA 1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
RC607 1 2 100K_0402_5% RC731 1 2 0_0201_5% DG35 DM19
SPI_IO2 @ PCH_SPI_IO2 SPI0_IO3 GPP_C1/SMBDATA PCH_SMB_ALERT# Notes:
RC730 1 2 0_0201_5% DJ39 DN19 1. The internal pull-down is disabled after RSMRST# de-asserts
SPI_SO @ PCH_SPI_SO SPI0_IO2 GPP_C2/SMBALERT#
RC609 1 @ 2 4.7K_0402_5% RC732 1 2 0_0201_5% DJ33 2.When used as PCHHOT# and strap low, a 150K pull-up
[44] SPI_SO SPI_SI @ PCH_SPI_SI SPI0_MISO PCH_SML0_CLK
RC729 1 2 0_0201_5% DJ35 DK19 is needed to ensure it does not override the internal pull-down
[44] SPI_SI PCH_SPI0_CS1# SPI0_MOSI GPP_C3/SML0CLK PCH_SML0_DATA strap sampling.
DF35 DM17
PCH_SPI0_CS0# SPI0_CS1# GPP_C4/SML0DATA PCH_SML0_ALERT# 3. This signal is in the primary well
DG37 DN17
D SPI0_CS0# GPP_C5/SML0ALERT# D
GPP_E6: DF39
SPI0_CS2#
DK17 PCH_SML1_CLK
JTAG ODT Disable BOARD_ID4 GPP_C6/SML1CLK PCH_SML1_DATA
Rising edge of RSMRST# DJ6 DJ17
BOARD_ID2 GPP_E11/THC0_SPI1_CLK GPP_C7/SML1DATA SML1_ALERT#
This strap does not have an internal pull-up or pull-down. DN5 CY50
BOARD_ID1 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
DR9
External pull-up is recommended BOARD_ID5 DM6
GPP_E1/THC0_SPI1_IO2
DN53 ESPI_CLK_R RC702 1 2 1/20W_49.9_1%_0201
0=> JTAG ODT is disabled BOARD_ID6 DK6
GPP_E12/THC0_SPI1_IO1 GPP_A5/ESPI_CLK
DJ53 ESPI_IO3_R RC706 1 2 1/20W_15_5%_0201
ESPI_CLK 44
1=> JTAG ODT is enabled BOARD_ID3 DK8
GPP_E13/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK#
DH50 ESPI_IO2_R RC705 1 2 1/20W_15_5%_0201
ESPI_IO3 44
GPP_E10/THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1_R ESPI_IO2 44
DV11 DP50 RC704 1 2 1/20W_15_5%_0201
44 EC_SMI BOARD_ID7 GPP_E8/SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO0_R ESPI_IO1 44
DW9 DP52 RC703 1 2 1/20W_15_5%_0201
GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS#_R ESPI_IO0 44
DT8 DK52 RC707 1 2 0_0201_5%
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_CS# 44
DL50 @
+3VALW_PCH BOARD_ID8 GPP_A6/ESPI_RESET# ESPI_RST# 44
DN15
BOARD_ID12 DK13 GPP_F11/THC1_SPI2_CLK
BOARD_ID11 DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 Board ID Table 1: 3.3V Level Board ID Table 1: 1.8V Level
BOARD_ID10 DN13 GPP_F14/GSXDIN/THC1_SPI2_IO2
BOARD_ID9 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 0 Non-FPR 00 Samsung ***
RPC701 DJ15 Board ID1 GPP_E1 No Use Board ID8 GPP_F11
4 1 PCH_SML0_CLK BOARD_ID13 DK15 GPP_F12/GSXDOUT/THC1_SPI2_IO0
PCH_SML0_DATA GPP_F16/GSXCLK/THC1_SPI2_CS# 1 FPR H 01 Micro ***
3 2 DN10
GPP_F18/THC1_SPI2_INT#
DV14
GPP_F17/THC1_SPI2_RST# 0 Non-TS 10 Hynix ***
2.2K_0404_4P2R_5% Board ID2 GPP_E2 No Use Board ID9 GPP_F12
RPC702 DH3
CL_CLK 1 TS L 11 No Use
GPP_C2(PCH_SMB_ALERT#): DH4
2 3 PCH_SML1_CLK CL_DATA
PCH_SML1_DATA This signal is used to wake the system or generate SMI#. DF2
CL_RST# 00 FHD *** 00 4G No Use
1 4 Board ID3 GPP_E10 Board ID10 GPP_F13
External Pull-up resistor is required.Rising edge of RSMRST#
This signal has a 20K+/-30% internal pull-down. H 01 UHD No Use H 01 8G ***
2.2K_0404_4P2R_5%
0 = Disable Intel ME Crypto Transport Layer Security (TLS)
PCH_SMB_ALERT# cipher suite (no confidentiality). (Default)
@ TGLLAKE-U_BGA1449 10 FHD HDR *** 10 12G ***
RC708 1 2 4.7K_0402_5% Board ID4 GPP_E11 Board ID11 GPP_F14
1 = Enable Intel ME Crypto Transport Layer Security (TLS) L 11 Reserved No Use L 11 16G ***
RC701 1 @ 2 4.7K_0402_5% PCH_SML0_ALERT# cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS. 00 13" No Use 0 OPT
Notes: Board ID5 GPP_E12 Board ID12 GPP_F15 No Use
1. The internal pull-down is disabled after RSMRST# de-asserts. H 01 14" *** 1 UMA
2. This signal is in the primary well. Reserved
10 15" *** 10 for
GPP_C5(PCH_SML0_ALERT#): Board ID6 GPP_E13 Board ID13 GPP_F16 dGPU
C
Rising edge of RSMRST# L 11 17" No Use 11 C

This signal has a 20K+/-30% internal pull-down.

0 = Enable eSPI. (Default) 0 Non-TPM
+3VALW_PCH Board ID7 No Use
1 = Disable eSPI. GPP_E17 No Use
+3VS 1 TPM
Notes: Reserved
1. The internal pull-down is disabled after RSMRST# de-asserts. +3VS for
+1.8VALW_PCH 2. This signal is in the primary well Project

4
3

4
3
1K_0402_5% 2 @ 1 RC709 ESPI_CS# RPC703 RPC704

2
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
75K_0402_1% 2 @ 1 RC710 +3VALW_PCH +3V_SPI
QC701A
BOARD ID

1
2

1
2
RC711 1 2 0_0402_5% @
PCH_SMB_CLK 6 1
SMB_CLK_S3 18

S
DC701 +1.8VALW_PCH +3VALW_PCH

D
2N7002KDWH_SOT363-6

5
2 1

G
2 1 QC701B
ESPI_RST# RC712 1 2 75K_0402_1% RB521CM-30T2R_VMN2M-2
PCH_SMB_DATA 3 4

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
@
SMB_DATA_S3 18

1
@ CC701 1 2 0.033UC_10VC_KC_X5RC_0201

RC833

RC832

RC831

RC830

RC829

RC828

RC827

RC826

RC825

RC824

RC823

RC822

RC821
D

1
2N7002KDWH_SOT363-6

PCH_SPI_CLK RC713 1 2 100K_0402_5%

@ @

NTS@

FP@
2

2
2
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
+3V_SPI BOARD_ID6
+3VALW_PCH BOARD_ID7
Internal 20K PD @PCH
BOARD_ID8
B VIH=0.7VCC @SPI ROM BOARD_ID9 B
1
BOARD_ID10
1/20W_4.7K_5%_0201 2 1 RC759 PCH_SPI0_CS0# CC702 BOARD_ID11
0.1U_6.3V_K_X5R_0201 BOARD_ID12
RC740 UC701 2 BOARD_ID13
PCH_SPI0_CS1# PCH_SPI0_CS1# @ SPI_16M_CS1#
150K_0402_5% 2 1 RC714 1 2 0_0201_5% 1 8
/CS VCC

1
100K_0201_5%
RC846

100K_0201_5%
RC845

100K_0201_5%
RC844

100K_0201_5%
RC843

100K_0201_5%
RC842

100K_0201_5%
RC841

100K_0201_5%
RC840

100K_0201_5%
RC839

100K_0201_5%
RC838

100K_0201_5%
RC837

100K_0201_5%
RC836

100K_0201_5%
RC835

100K_0201_5%
RC834
1

1
SPI_SO 1/20W_15_5%_0201 1 2 RC741 SPI_16M_SO 2 7 SPI_16M_IO3 RC743 1 2 1/20W_15_5%_0201 SPI_IO3
1/20W_4.7K_5%_0201 1 2 RC716 PCH_SPI_SI DO(IO1) /HOLD(IO3)
SPI_IO2 1/20W_15_5%_0201 1 2 RC742 SPI_16M_IO2 3 6 SPI_16M_CLK RC744 1 2 1/20W_15_5%_0201 SPI_CLK
100K_0402_5% 2 1 RC718 PCH_SPI_IO2 /WP(IO2) CLK

TS@

NON_FP@
2
4 5 SPI_16M_SI RC745 1 2 1/20W_15_5%_0201 SPI_SI @ @ @ @ @ @ @ @

@
GND DI(IO0)

2
100K_0402_5% 2 1 RC720 PCH_SPI_IO3

PCH_SPI_SI / PCH_SPI_WP#(IO2) / PCH_SPI_HOLD#(IO3): W25Q128JVSIQ_SO8

External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
+3V_SPI
This strap should sample HIGH. There should NOT be
14" 00(R839,R838)
any on-board device driving it to opposite direction BOARD_ID5..4 15" 01(R839,R825)
during strap sampling. 17" 10(R826,R838)
1
Sumsang 0000
CC1446 BOARD_ID6/7/8/9 Hynix 0001
0.1U_6.3V_K_X5R_0201 Micron 0010
RC746 UC703 2
SPI_CS0# @ SPI_8M_CS0#
1 2 0_0201_5% 1 8
SPI_SO 1/20W_15_5%_0201 1 2 RC747 SPI_8M_SO 2 /CS VCC 7 SPI_8M_IO3 RC748 1 2 1/20W_15_5%_0201 SPI_IO3
SPI_IO2 1/20W_15_5%_0201 1 2 RC749 SPI_8M_IO2 3 IO1 IO3 6 SPI_8M_CLK RC750 1 2 1/20W_15_5%_0201 SPI_CLK
4 IO2 CLK 5 SPI_8M_SI RC751 1 2 1/20W_15_5%_0201 SPI_SI
RC739 GND IO0
@ PCH_SPI0_CS1#
1 2 0_0201_5% W25R64JVSSIQ_SO8
[44] SPI_CS#
RPMC_8M_ROM@
RC752 1 @ 2 0_0201_5%
[44] SPI_CS#
UC702
RC735 1 8
PCH_SPI0_CS0# @ SPI_CS0# /CS VCC
1 2 0_0201_5%
A 2 7 A
DO (IO1) IO3
3 6
SPI_SO RC733 1 @ 2 100K_0201_5% IO2 CLK
4 5
GND DI (IO0)

W25Q64JVSSIQ_SO8
8M_ROM@

Security Classification LC Future Center Secret Data Title

UC703 ,UC702 co-lay
Issued Date 2018/12/04 Deciphered Date 2018/08/20 SPI/SMB/SML/ESPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

Need support wake by touch pad

+3VALW_PCH
RPC801
PCH_I2C1_SDA_TP 1 4
PCH_I2C1_SCL_TP 2 3

UC1F 2.2K_0404_4P2R_5%
PCH_TP_INT# RC801 1 2 10K_0402_5%
6 OF 21

@
PCH_TP_INT# DC53 DR27 RC2023 1 FPR_DELINK
2 0_0201_5% +3VS
44,45 PCH_TP_INT# GPP_B18 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD FPR_DELINK 45
DA51 DW27 ECLPM_BREAK [44]
D PCH_WLAN_PERST#DC49 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD UART2_TXD RC802 1 2 49.9K_0402_1% D
40 PCH_WLAN_PERST# DV25
PCH_BEEP GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# FPR_RESET_C RC852 1 2 0_0402_5% @ UART2_RXD RC803 1 2 49.9K_0402_1%
30 PCH_BEEP DC50 DT25 FPR_RESET 45
PCH_WLAN_OFF# DC52 GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 RC854
40 PCH_WLAN_OFF# GPP_B15/GSPI0_CS0# @
DB45 1 2 0_0201_5% FB_GC6_EN_R FPR_DELINK RC890 1 @ 2 2.2K_0402_5%
GPP_B6/ISH_I2C0_SCL GPU_EVENT# FB_GC6_EN_R [23,26]
RC848 CY49 DB44
@ PCH_TS_EN_R GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA GPU_EVENT# [26]
1 2 0_0201_5% CY53
[33] PCH_TS_EN GPP_B22/GSPI1_MOSI PXS_PWREN_R RC804
CY52 CY39 1 OPT@ 2 0_0402_5%
VCC_TS_ON GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL PXS_RST#_R RC805 PXS_PWREN [23]
DA50 DB47 1 OPT@ 2 0_0402_5%
[33] VCC_TS_ON GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA PXS_RST# [26]
DV21 DD47 DGPU_PWROK_R RC806 1 OPT@ 2 0_0402_5%
GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL DGPU_PWROK [23,58]
DT21 DD44
GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
DR21
GPP_C11/UART0_CTS#
DW21 DJ8
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7
DR7
RC856 GPP_E15/ISH_GP6
@ DV19 DR24
1 2 0_0201_5% PCH_CAPS_LED# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5
[45] CAPS_LED# DT19 DU25
RC855 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4
@ DR18 DV31
1 2 0_0201_5% GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3
[45] NUM_LED# DU19 DU31
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2
DT27
UART2_TXD GPP_D1/ISH_GP1/BK1/SBK1
DJ21 DV27
UART2_RXD GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
DEBUG
PCIE_WAKE#_WLAN_R
DG23
GPP_C20/UART2_RXD GPP_RCOMP
40 PCIE_WAKE#_WLAN_R DJ19 DR51
GPP_C23/UART2_CTS# GPP_RCOMP

1
DF21
GPP_C22/UART2_RTS# RC2021
DN33
GPP_T3
DV18 DT35 1/20W_200_1%_0201
GPP_C17/I2C0_SCL GPP_T2
TS DW18
GPP_C16/I2C0_SDA
DG17
GPP_U5

2
PCH_I2C1_SCL_TP DJ23 DG19
45 PCH_I2C1_SCL_TP PCH_I2C1_SDA_TP GPP_C19/I2C1_SCL GPP_U4 +3VS
TP 45 PCH_I2C1_SDA_TP DT18
GPP_C18/I2C1_SDA
DJ29 PXS_PWREN_R RC807 1 OPT@ 2 10K_0201_5%
GPP_H5/I2C2_SCL
SENSOR DJ31
GPP_H4/I2C2_SDA RC808 1 @ 2 10K_0201_5%
DF29
GPP_H7/I2C3_SCL
DG29
GPP_H6/I2C3_SDA
DF25
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
C DF27 C
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD +3VS

PXS_RST#_R RC809 1 @ 2 10K_0201_5%

TGLLAKE-U_BGA1449
@ RC810 1 OPT@ 2 10K_0201_5%

RC811 1 @ 2 100K_0201_5% PCH_WLAN_PERST#

FB_GC6_EN_R RC812 1 @ 2 10K_0201_5%

+3VS
+3VS +3VS
GPU_EVENT# RC813 1 OPT@ 2 10K_0201_5%
+3VALW_PCH RC815 1 @ 2 4.7K_0402_5% PCH_BEEP RC816 1 @ 2 1/20W_4.7K_5%_0201 GPP_B18
RC817 1 @ 2 10K_0201_5%
RC847 1 2 100K_0201_5% ECLPM_BREAK GPP_B14(PCH_BEEP): RC819 1 @ 2 1/20W_20K_5%_0201
Rising edge of PCH_PWROK
The strap has a 20 kohm ± 30% internal pull-down.
0 = Disable Top Swap mode. (Default) PXS_RST# 1 2 0.01U_6.3V_K_X7R_0201
1 = Enable Top Swap mode. This inverts an address on access to SPI GPP_B18:Rising edge of PCH_PWROK CC801
and firmware hub, so the processor believes it fetches the alternate The signal has a weak internal pull-down.
0 = Disable No Reboot mode. (Default) OPT@
boot block instead of the original boot-block. PCH will invert A16
(default) for cycles going to the upper two 64-KB blocks in the FWH 1 = Enable No Reboot mode (PCH will disable the
or the appropriate address lines (A16, A17, or A18) as selected TCO Timer system reboot feature). This function is
in Top Swap Block size soft strap. useful when running ITP/XDP. DGPU_PWROK RC820 1 UMA@ 2 10K_0201_5%
Notes: Notes:
1. The internal pull-down is disabled after CC1445 1 2 0.01U_6.3V_K_X7R_0201
1. The internal pull-down is disabled after PCH_PWROK is high.
2. Software will not be able to clear the Top Swap bit until the system PCH_PWROK is high. EMC_NS@
is rebooted. 2. This signal is in the primary well.
3. The status of this strap is readable using the Top Swap bit
B (Bus0, Device31, Function0, offset DCh, bit4). B
4. This signal is in the primary well.

+3VS

CAPS_LED# RC857 1 2 100K_0201_5%

NUM_LED# RC859 1 2 100K_0201_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 UART/I2C/ISH/GSPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document Name
Document Name Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
9 OF 21

BT7 CV4 USB20_P10

PCIE12_TXP/SATA1_TXP USB2P_10 USB20_P10 40
BT8
CE2
PCIE12_TXN/SATA1_TXN USB2N_10
CY3 USB20_N10
USB20_N10 40 BT
PCIE12_RXP/SATA1_RXP
CE1 DD5
PCIE12_RXN/SATA1_RXN USB2P_9
DD4
D SATA_PTX_DRX_P0 USB2N_9 D
[37] SATA_PTX_DRX_P0 BT9
SATA_PTX_DRX_N0 PCIE11_TXP/SATA0_TXP
[37] SATA_PTX_DRX_N0 BV9 CW9
SATA_PRX_DTX_P0 PCIE11_TXN/SATA0_TXN USB2P_8
HDD [37]
[37]
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PRX_DTX_N0
CF4
CF3
PCIE11_RXP/SATA0_RXP
PCIE11_RXN/SATA0_RXN
USB2N_8
DA9

DD1 USB20_P7
USB2P_7 USB20_N7 USB20_P7 45
BV7
PCIE10_TXP USB2N_7
DD2 USB20_N7 45 Finger Print
BV8
PCIE10_TXN USB20_P6
CG2 DA1
CG1
PCIE10_RXP
PCIE10_RXN
USB2P_6
USB2N_6
DA2 USB20_N6 USB20_P6
USB20_N6
30
30 Card reader
CC906 1 20.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_P9 BY7 USB20_P5
[40] PCIE_PTX_C_DRX_P9
CC905 1 20.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_N9 BY8 PCIE9_TXP USB2P_5
DA12
USB20_N5 USB20_P5 33 Camera
WLAN [40]
[40]
PCIE_PTX_C_DRX_N9
PCIE_PRX_DTX_P9
PCIE_PRX_DTX_P9 CG5 PCIE9_TXN
PCIE9_RXP
USB2N_5
DA11 USB20_N5 33
PCIE_PRX_DTX_N9 CG4 DC8 USB20_P4
[40] PCIE_PRX_DTX_N9 PCIE9_RXN USB2P_4 USB20_P4 42
PCIE_PTX_DRX_P8 CB8
USB2N_4
DC7 USB20_N4
USB20_N4 42 USB2.0
[37] PCIE_PTX_DRX_P8 PCIE_PTX_DRX_N8 PCIE8_TXP USB20_P3
CB7 DB4
[37]
[37]
PCIE_PTX_DRX_N8
PCIE_PRX_DTX_P8
PCIE_PRX_DTX_P8
PCIE_PRX_DTX_N8
CK5
PCIE8_TXN
PCIE8_RXP
USB2P_3
USB2N_3
DB3 USB20_N3 USB20_P3
USB20_N3
33
33 Touch Screen
[37] PCIE_PRX_DTX_N8 CK4
PCIE8_RXN USB20_P2
DA5
[37] PCIE_PTX_DRX_P7
PCIE_PTX_DRX_P7
PCIE_PTX_DRX_N7
CD9
PCIE7_TXP
USB2P_2
USB2N_2
DA4 USB20_N2 USB20_P2
USB20_N2
41
41 USB3.0 Port1
[37] PCIE_PTX_DRX_N7 CD8
PCIE_PRX_DTX_P7 PCIE7_TXN USB20_P1
[37] PCIE_PRX_DTX_P7 CK1 DC11
[37] PCIE_PRX_DTX_N7
PCIE_PRX_DTX_N7 CK2
PCIE7_RXP
PCIE7_RXN
USB2P_1
USB2N_1
DC9 USB20_N1 USB20_P1
USB20_N1
41
41 USB3.0 Port2
SSD PCIE_PTX_DRX_P6 CG8
PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
DP4
[37] PCIE_PTX_DRX_P6 PCIE_PTX_DRX_N6 CG7 DF41 SSD_PCIE_DET#
[37] PCIE_PTX_DRX_N6 PCIE_PRX_DTX_P6 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM SSD_PCIE_DET# [37]
CL4
[37] PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 PCIE6_RXP USB_OC0#
CL3 DD8 USB_OC0# 41
[37] PCIE_PRX_DTX_N6 PCIE6_RXN GPP_E9/USB_OC0#
DJ45 USB_OC3#
PCIE_PTX_DRX_P5 GPP_A16/USB_OC3#/I2S4_SFRM
CJ8
[37] PCIE_PTX_DRX_P5 PCIE_PTX_DRX_N5 PCIE5_TXP
CJ7 DN6
[37] PCIE_PTX_DRX_N5 PCIE_PRX_DTX_P5 PCIE5_TXN GPP_E5/DEVSLP1
CN2 DG8
[37] PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 PCIE5_RXP GPP_E4/DEVSLP0
CN1
PCIE5_RXN TBT
[37] PCIE_PRX_DTX_N5 DN29
GPP_H15/M2_SKT2_CFG3
CR8 DK29
CR7
PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2
DT31 Type-C B
PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1
C CN5 DR32 C
PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0
CN4
PCIE4_RXN/USB31_4_RXN
DV9 PCIE_RCOMPP 1/20W_100_1%_0201 2 1 RC905
PCIE_RCOMP_P
CU8 DT9 PCIE_RCOMPN
PCIE3_TXP/USB31_3_TXP PCIE_RCOMP
CU7
PCIE3_TXN/USB31_3_TXN USB2_VBUSSENSE RC902 1 2 10K_0201_5%
CT2 DC12
PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE USB2_ID RC901 1 2 10K_0201_5%
CT1 DF1
PCIE3_RXN/USB31_3_RXN USB_ID USB2_COMP RC903 1 2 1/16W_113_1%_0402
DE1
USB30_TX_P2 USB2_COMP
41 USB30_TX_P2 CW8
USB30_TX_N2 PCIE2_TXP/USB31_2_TXP
41 USB30_TX_N2 CW7 E3
USB30_RX_P2 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN
USB3.0 Port2 41 USB30_RX_P2 CU3
USB30_RX_N2 PCIE2_RXP/USB31_2_RXP
41 USB30_RX_N2 CT4
PCIE2_RXN/USB31_2_RXN
USB30_TX_P1
DA8
41 USB30_TX_P1 USB30_TX_N1DA7 PCIE1_TXP/USB31_1_TXP
41 USB30_TX_N1 USB30_RX_P1 PCIE1_TXN/USB31_1_TXN
USB3.0 Port1 41 USB30_RX_P1 CV2
USB30_RX_N1CV1
PCIE1_RXP/USB31_1_RXP
41 USB30_RX_N1 PCIE1_RXN/USB31_1_RXN

TGLLAKE-U_BGA1449
@

+3VALW_PCH

RC904 1 2 10K_0201_5% USB_OC0#

+1.8VALW_PCH

RC906 1 2 10K_0201_5% USB_OC3#

RC907 1 2 10K_0201_5% SSD_PCIE_DET#

B B

UC1H
8 OF 21

PCIE4_CTX_C_GRX_P3 OPT@ 0.22U_0201_6.3V6-K 1 2 CC902 PCIE4_CTX_GRX_P3 P5 V5 PCIE4_CTX_GRX_P1 CC908 2 1 0.22U_0201_6.3V6-K OPT@ PCIE4_CTX_C_GRX_P1
PCIE4_CTX_C_GRX_N3 OPT@ 0.22U_0201_6.3V6-K 1 2 CC901 PCIE4_CTX_GRX_N3 P7 PCIE4_TX_P_3 PCIE4_TX_P_1 PCIE4_CTX_GRX_N1 CC907 2 1 0.22U_0201_6.3V6-K OPT@ PCIE4_CTX_C_GRX_N1
20 PCIE4_CRX_GTX_N[0..3] V7
PCIE4_CRX_GTX_P3 N1 PCIE4_TX_N_3 PCIE4_TX_N_1 PCIE4_CRX_GTX_P1
T1
PCIE4_CRX_GTX_N3 N2 PCIE4_RX_P_3 PCIE4_RX_P_1 PCIE4_CRX_GTX_N1
dGPU
20 PCIE4_CRX_GTX_P[0..3] T2
PCIE4_RX_N_3 PCIE4_RX_N_1

20 PCIE4_CTX_C_GRX_N[0..3]
PCIE4_CTX_C_GRX_P2
PCIE4_CTX_C_GRX_N2
OPT@ 0.22U_0201_6.3V6-K 1
OPT@ 0.22U_0201_6.3V6-K 1
2
2
CC904
CC903
PCIE4_CTX_GRX_P2 T5
PCIE4_CTX_GRX_N2 T7 PCIE4_TX_P_2 PCIE4_TX_P_0
Y5
Y7
PCIE4_CTX_GRX_P0
PCIE4_CTX_GRX_N0
CC910
CC909
2
2
1 0.22U_0201_6.3V6-K OPT@
1 0.22U_0201_6.3V6-K OPT@
PCIE4_CTX_C_GRX_P0
PCIE4_CTX_C_GRX_N0
dGPU
PCIE4_CRX_GTX_P2 R1 PCIE4_TX_N_2 PCIE4_TX_N_0 PCIE4_CRX_GTX_P0
20 PCIE4_CTX_C_GRX_P[0..3] V1
PCIE4_CRX_GTX_N2 R2 PCIE4_RX_P_2 PCIE4_RX_P_0 PCIE4_CRX_GTX_N0
V2
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMP_P
PCIE4_RCOMP_P
V12 PCIE4_RCOMP_N RC2022 1 2
PCIE4_RCOMP V12 2.2K_0402_1%

@ TGLLAKE-U_BGA1449

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 PCIE/SATA/USB3/USB2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1J
10 OF 21

D22 DK47 CNV_WT_D1P

CSI_F_DP_1 CNVI_WT_D1P CNV_WT_D1N CNV_WT_D1P 40
B22 DM47 CNV_WT_D1N 40
CSI_F_DN_1 CNVI_WT_D1N CNV_WT_D0P +1.8VALW_PCH
E22 DN49 CNV_WT_D0P 40
CSI_F_DP_0 CNVI_WT_D0P CNV_WT_D0N
D20 DR49 CNV_WT_D0N 40
CSI_F_DN_0 CNVI_WT_D0N CNV_WT_CLKP CNVI_RGI_RSP RC1000 1 @ 2 20K_0402_5%
A20 DN45 CNV_WT_CLKP 40
CSI_F_CLK_P CNVI_WT_CLKP CNV_WT_CLKN
B20 DN47 CNV_WT_CLKN 40
CSI_F_CLK CNVI_WT_CLKN CNVI_BRI_RSP RC1001 1 @ 2 20K_0402_5%
B18 DU43 CNV_WR_D1P
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P CNV_WR_D1N CNV_WR_D1P 40
A18 DV43 CNV_WR_D1N 40
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_WR_D0P
D18 DR44 CNV_WR_D0P 40
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_WR_D0N
E18 DT43 CNV_WR_D0N 40
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CNV_WR_CLKP
C16 DV44 CNV_WR_CLKP 40
CSI_E_CLK_P CNVI_WR_CLKP CNV_WR_CLKN +1.8VALW_PCH
D16 DW44 CNV_WR_CLKN 40
CSI_E_CLK CNVI_WR_CLKN
D CNV_WT_RCOMP RC1005 1 D
D15 DN51 2 150_0402_1% RC1002 1 @ 2 4.7K_0402_5%
CSI_C_DP_2 CNVI_WT_RCOMP
E15
CSI_C_DN_2 CNVI_RGI_RSP CNVI_BRI_DT_R RC1004 1 @ 2 1/20W_20K_5%_0201
A15 DJ13 @ CNVI_RGI_RSP 40
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNVI_RGI_DT_R RC1006 1 2 0_0201_5%
B15 DG13 CNVI_RGI_DT 40
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD CNVI_BRI_RSP
DF15 @ CNVI_BRI_RSP 40
GPP_F1/CNV_BRI_RSP/UART0_RXD CNVI_BRI_DT_R RC1007 1 2 0_0201_5%
L18 DF17 CNVI_BRI_DT 40
CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
N18
CSI_C_DN_1 GPP_F0 /CNV_BRI_DT /UART0_RTS#
L20 DJ10 XTAL Frequency Selection, Rising edge of RSMRST#
CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ
N20 DV15 This strap has a 20 kohm ± 30% internal pull-down.
CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING
G20 DK10 This strap should not be pulled high since 24 MHz crystal is not
CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
H20
CSI_C_CLK supported on the PCH.
H16 0 = 38.4 MHz (default)
G16
CSI_B_DP_1 1 = 24 MHz
CSI_B_DN_1 Notes:
G18
CSI_B_DP_0 1. The internal pull-down is disabled after RSMRST# de-asserts.
H18
CSI_B_DN_0 2. This signal is in the primary well.
L16
CSI_B_CLK_P
N16
CSI_B_CLK
G14
CSI_B_DP_2
H14
CSI_B_DN_2 +1.8VALW_PCH
L14
CSI_B_DP_3 @
N14
CSI_B_DN_3 CNVI_RGI_DT_R RC1009 1 2 100K_0402_5%
RC1008 1 2 150_0402_1% CSI2_COMP K14
CSI_RCOMP RC1011 1 @ 2 4.7K_0402_5%
DK25
GPP_H23/IMGCLKOUT4
DM25
GPP_H22/IMGCLKOUT3
DN25
GPP_H21/IMGCLKOUT2
DJ25
GPP_H20/IMGCLKOUT1 GPP_F2 /CNV_RGI_DT /UART0_TXD:
DR30
GPP_D4/IMGCLKOUT_0/BK4/SBK4 M.2 CNVI MODES, Rising edge of RSMRST#
A weak external pull-up is required.
0 = Integrated CNVi enabled.
1 = Integrated CNVi disabled.
@ TGLLAKE-U_BGA1449
Note:
When a RF companion chip is connected to the PCH CNVi interface,
C +3VS the device internal pulldown resistor will pull the strap low to C
enable CNVi interface.
10K_0201_5% 2 @ 1 RC1012 WLAN_CLKREQ#

10K_0201_5% 2 1 RC1013 SSD_CLKREQ#

10K_0201_5% 2 1 RC1014 GPU_CLKREQ#

UC1K
11 OF 21

BW1 DU14
CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6#
BW2 DF23
CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5#
DG25
GPP_H10/SRCCLKREQ4#
CB2 DT24
CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# WLAN_CLKREQ#
CB1 DT30 WLAN_CLKREQ# [40]
CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# SSD_CLKREQ#
DV30 SSD_CLKREQ# [37]
GPP_D6/SRCCLKREQ1# GPU_CLKREQ#
DW30 GPU_CLKREQ# [20]
GPP_D5/SRCCLKREQ0#
BW4
CLKOUT_PCIE_P4 XTAL_PCH_38P4M_OUT
BW5 DM1
CLKOUT_PCIE_N4 XTAL_OUT XTAL_PCH_38P4M_IN
DL1
XTAL_IN
CL7
CLKOUT_PCIE_P3
CL8 DW41 SUSCLK SUSCLK 40
CLKOUT_PCIE_N3 GPD8/SUSCLK
CLK_PCIE_WLAN CB4 DT47 RTC_X2
40 CLK_PCIE_WLAN CLK_PCIE_WLAN# CLKOUT_PCIE_P2 RTCX2 RTC_X1
40 CLK_PCIE_WLAN# CB5 DR47
CLKOUT_PCIE_N2 RTCX1
CLK_PCIE_SSD BY4 DN37 RTC_RST#
37 CLK_PCIE_SSD CLK_PCIE_SSD# CLKOUT_PCIE_P1 RTCRST# SRTC_RST#
37 CLK_PCIE_SSD# BY3 DK37
CLKOUT_PCIE_N1 SRTCRST#
CLK_PCIE_GPU CN7
20 CLK_PCIE_GPU CLK_PCIE_GPU# CLKOUT_PCIE_P0
20 CLK_PCIE_GPU# CN8
CLKOUT_PCIE_N0
1/20W_60.4_1%_02012 1 RC1016 XCLK_BIASREFDJ5
XCLK_BIASREF 1K_0402_5% 2 @ 1 RC1015 SUSCLK

@ TGLLAKE-U_BGA1449
B B

XTAL_PCH_38P4M_IN RC1017 1 2 0_0402_5% XTAL_PCH_38P4M_IN_R

LC1000
4 3
4 3

1 2
1 2
EXC24CH500U_4P
EMC_NS@

XTAL_PCH_38P4M_OUT RC1021 1 2 0_0402_5% XTAL_PCH_38P4M_OUT_R

RTC_X1

RTC_X2
1
XTAL_PCH_38P4M_IN_R 1
RC1023 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R VCCRTC CC1000
RC1022 1 2 10M_0402_5% 1U_6.3V_K_X5R_0201
YC1001 YC1000 RC1018 1 2 20K_0402_1% 2 RTC_RST# RC1019 1 2 0_0402_5% @
EC_RTC_RST# 44
1 2
4 3 RC1020 1 2 20K_0402_1% SRTC_RST#
NC1 OSC2 32.768KHZ 9PF 202934-PG14 1
1 2 1 1 CC1001
OSC1 NC2 1U_6.3V_K_X5R_0201
A 1 1 CC1002 CC1003 A
CC1004 CC1005 8.2P_50V_J_NPO_0402 9P_50V_C_COG_0402 2
38.4MHZ_10PF_7R38400001 2 2
10P_0402_50V8J 10P_0402_50V8J
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 CSI/EMMC/CNVI/CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

UC1L
12 OF 21

PM_SLP_SUS# DV49 BM9

44 PM_SLP_SUS# SLP_SUS# PROCPWRGD PBTN_OUT#_R
DK41 PBTN_OUT#_R 44
PM_SLP_S5# GPD3/PWRBTN# BATLOW# 1
DM43 DN41
PM_SLP_S4# GPD10/SLP_S5# GPD0/BATLOW# AC_PRESENT_R TP1102 @
44 PM_SLP_S4# DJ41 DK43 AC_PRESENT_R 44
PM_SLP_S3# GPD5/SLP_S4# GPD1/ACPRESENT
44 PM_SLP_S3# DJ43
PM_SLP_A# GPD4/SLP_S3#
DR41 CW40 PCH_PMC_ALERT_N
PM_SLP_WLAN# GPD6/SLP_A# GPP_B11/PMCALERT# CPU_C10_GATE#
40 PM_SLP_WLAN# DT44 DN27 CPU_C10_GATE# [46]
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# SX_EXIT_HOLDOFF# 1 TP1101 @
DG31
PM_SLP_S0# GPP_H3/SX_EXIT_HOLDOFF#
44,43 PM_SLP_S0# DD42
PM_SLP_LAN# GPP_B12/SLP_S0#
DN39 DK39 PCIE_WAKE# 40
SLP_LAN# WAKE#
PCH_RSMRST#_R DM35 DM41 PCH_LAN_WAKE#
SYS_RESET# RSMRST# GPD2/LAN_WAKE# PCH_CNVI_EN# RC1100 1 2 0_0402_5% @
DD10 DT41 CNVI_EN# 40
D
RC1101 1 2 0_0201_5% @ PLT_RST#_R SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON D
26,37,40,44 PLT_RST# DD41
GPP_B13/PLTRST# BB_TBT_PERST_N
DN43
PCH_DPWROK_R DK35 GPD7
RC1105 1 2 0_0201_5% @ SYS_PWROK_R DSW_PWROK VCCSTPWRGOOD_TCSS RC1102 1 2 0_0201_5% @ VCCST_OVERRIDE
44 SYS_PWROK DF10 CE5 VCCST_OVERRIDE 46
RC1106 1 2 0_0201_5% @ PCH_PWROK_R SYS_PWROK VCCSTPWRGOOD_TCSS VCCST_PWRGD_R RC1103 1 2 60.4_0402_1%
44 PCH_PWROK DN35 BP8 EC_VCCST_PWRGD 44
PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE_R RC1104 1 2 0_0201_5%
BP9
INTRUDER# VCCST_OVERRIDE @
DM37
SPIVCCIOSEL INTRUDER#
DT49 DR12
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE#
DW12
GPP_F21/EXT_PWR_GATE2#

@ TGLLAKE-U_BGA1449 BB_TBT_PERST_N RC184 1 2 1/20W_20K_5%_0201

DSW_PWROK and RSMRST# are always separate power good signals +3VALW

2
PCH_DPWROK RC1107 1 2 0_0402_5% @ PCH_DPWROK_R RC1135 EC_VCCST_PWRGD
44 PCH_DPWROK
100K_0201_5%
RC1108 2 1 100K_0201_5% @

3
D
5 QC1101B
EC_RSMRST# RC1109 1 2 0_0402_5% @ PCH_RSMRST#_R G
44 EC_RSMRST# 2N7002KDWH_SOT363-6

6
D
RC1110 2 1 100K_0201_5% PM_SLP_S3# 2 S @

4
G

S QC1101A

1
2N7002KDWH_SOT363-6
@
C C
+3VALW_PCH

RC1111 2 @ 1 4.7K_0402_5% SPIVCCIOSEL +VCCST_CPU

RC1112 2 1 4.7K_0402_5% EC_VCCST_PWRGD RC1113 1 2 1K_0402_5%

Glitch Free Requirements:

CAD NOTE: Pull-up resistor is required if a device is monitoring SLP_S0#
INPUT3VSEL: 3V SELECT STRAP before RSMRST# de-assertion +3VS
LOW-> 3.3V +/-5% 100K for 3.3V Signaling Mode SYS_RESET# RC1114 1 2 10K_0201_5%
HIGH->3.0V +/-5% 75K for 1.8V Signaling Mode
+3VALW_PCH

PM_SLP_S0# RC1115 1 2 100K_0201_5%

+VCCPDSW_3P3

PCIE_WAKE# RC1116 1 2 10K_0201_5%

VCCRTC
Glitch Free Requirements: PCH_LAN_WAKE# RC1117 1 2 10K_0402_5%
RC1118 1 2 1M_0402_5% INTRUDER# Cap or pull-down resistor is required PBTN_OUT#_R RC1119 1 @ 2 100K_0201_5%
Option 1:Cap Implementation
BATLOW# RC1120 1 2 100K_0201_5%
RC1121 1 2 1M_0402_5% 330 nF for 3.3v Ramp Rate from 5-50ms
@ INTRUDER# 33 nF for 3.3V Ramp Rate Less than 5ms AC_PRESENT_R RC1122 1 2 100K_0402_5%
RTC-Well Input Strap Requirements
should have a weak external pull-up to VccRTC Option 2:Pull-down Resistor Implementation
2
CC1100 1 0.1U_6.3V_K_X5R_0201
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

SPI Voltage Configuration:

PM_SLP_SUS# RC1126 1 2 100K_0201_5% +3VALW_PCH
The VCCSPI voltage (3.3V or 1.8V) is selected via a hard strap
B on the INTRUDER#. B
@ CC1101 1 2 0.033UC_10VC_KC_X5RC_0201
This strap sets the SPI interface signaling voltage at the rising edge CPU_C10_GATE# RC1123 1 @ 2 1/20W_20K_5%_0201
of RTCRST#. Designers should strap this pin to match the expected
interface operational voltage for their target SPI device as follows. PM_SLP_S3# RC1128 1 2 100K_0201_5%
0 = SPI interface operation voltage is 3.3V
(ground through a 10kohm resistor) @ CC1102 1 2 0.033UC_10VC_KC_X5RC_0201
1 = SPI interface operation voltage is 1.8V
(pulled up with 1 Mohm to VCCRTC)
PM_SLP_S4# RC1129 1 2 100K_0201_5%
PCH_PWROK RC1124 1 2 10K_0201_5%
@ CC1103 1 2 0.033UC_10VC_KC_X5RC_0201
SYS_PWROK RC1125 1 2 10K_0201_5%
PCH_RSMRST#_R CC1107 2 1 1000P_0201_50V7-K EMC_NS@ PM_SLP_A# @ RC1130 1 2 100K_0201_5% VCCST_OVERRIDE RC1127 1 2 100K_0402_5%
PCH_DPWROK_R CC1109 2 1 1000P_0201_50V7-K EMC_NS@ @ CC1104 1 2 0.033UC_10VC_KC_X5RC_0201
SYS_RESET# CC1444 2 1 1000P_0201_50V7-K EMC_NS@
PM_SLP_WLAN# @ RC1131 1 2 100K_0201_5%
FOR EMC
@ CC1105 1 2 0.033UC_10VC_KC_X5RC_0201 +3VALW_PCH
RC169
PCH_PMC_ALERT_N 1 2
PM_SLP_LAN# @ RC1132 1 2 100K_0201_5%

@ CC1106 1 2 0.033UC_10VC_KC_X5RC_0201 1K_0201_5%

PM_SLP_S5# @ RC1133 1 2 100K_0201_5%

@ CC1108 1 2 0.033UC_10VC_KC_X5RC_0201

PLT_RST# RC1134 1 2 100K_0201_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 MANAGEMENT-CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

UC1M
UC1O
13 OF 21
+VCCIN +VCCIN
15 OF 21
+1.2V
A24 G32
VCCIN_1 VCCIN_66 +VCCST_CPU
A26 H24 AA39 AF9 +VCCSTG_OUT_R
VCCIN_2 VCCIN_67 VDD2_1 VCCSTG_OUT_1
A29 H26 AB40 AF12
VCCIN_3 VCCIN_68 RC1201 1 2 100_0402_1% VR_SVID_DATA VDD2_2 VCCSTG_1
A30 H30 AC39 AD12
VCCIN_4 VCCIN_69 VDD2_3 VCCSTG_2
A33 H32 AD40
VCCIN_5 VCCIN_70 RC1202 1 2 56_0402_5% VR_SVID_ALERT# VDD2_4
A35 J1 AD51 AN10 +VCCSTG_OUT
VCCIN_6 VCCIN_71 VDD2_5 VCCSTG_OUT_2
AY39 J2 AD52 AM9
VCCIN_7 VCCIN_72 RC1203 1 @ 2 1/16W_45.3_1%_0402VR_SVID_CLK VDD2_6 VCCSTG_OUT_3
B24 K1 AE39 AG10
VCCIN_8 VCCIN_73 VDD2_7 VCCSTG_OUT_4
B26 K2 AF40
VCCIN_9 VCCIN_74 VDD2_8 INTERNAL RAIL.
B29
VCCIN_10 VCCIN_75
K24 CAD NOTE: AG39
VDD2_9 VCCIO_OUT
V15 +VCCIO_OUT
B30 K26 Alert signal must be routed between Clk and Data signals AH40
VCCIN_11 VCCIN_76 VDD2_10
B33 K30 to minimize Cross-Talk. AJ39 M9 +VCCSTG_OUT_LGC
VCCIN_12 VCCIN_77 VDD2_11 VCCSTG_OUT_LGC
B35 K32 AK40
D VCCIN_13 VCCIN_78 VDD2_12 D
BA10 L24 AK51 BT2 +VCCST_CPU
VCCIN_14 VCCIN_79 VDD2_13 VCCST_1
BA40 L26 AK52 BT1
VCCIN_15 VCCIN_80 VDD2_14 VCCST_2
BB39 L30 AL39 BT4
VCCIN_16 VCCIN_81 VDD2_15 VCCST_3
BB9 L32 AM40
VCCIN_17 VCCIN_82 VDD2_16
BC10 N24 AN39 BP2 +VCCSTG_CPU
VCCIN_18 VCCIN_83 VDD2_17 VCCSTG_3
BC40 N26 AP40 BP1
VCCIN_19 VCCIN_84 VDD2_18 VCCSTG_4
BD39 N30 AR39 BP4
VCCIN_20 VCCIN_85 VDD2_19 VCCSTG_5
BD9 N32 AT52
VCCIN_21 VCCIN_86 VDD2_20
BE10 P24 AU40
VCCIN_22 VCCIN_87 VDD2_21
BE40 P26 AW40
VCCIN_23 VCCIN_88 VDD2_22
BF9 P28 AW51
VCCIN_24 VCCIN_89 VDD2_23
BG10 P30 AW52
VCCIN_25 VCCIN_90 VDD2_24
BG40 P32 BD51
VCCIN_26 VCCIN_91 VDD2_25
BH12 T21 BD52
VCCIN_27 VCCIN_92 VDD2_26
BH39 T23 BK51
VCCIN_28 VCCIN_93 VDD2_27
BH9 T25 BK52
VCCIN_29 VCCIN_94 VDD2_28
BJ10 T27 BV51
VCCIN_30 VCCIN_95 VDD2_29
BJ40 T31 BV52
VCCIN_31 VCCIN_96 VDD2_30
BK39 U23 CA40
VCCIN_32 VCCIN_97 VDD2_31
BL10 U27 CC40
VCCIN_33 VCCIN_98 VDD2_32
BL40 U29 CC49
VCCIN_34 VCCIN_99 VDD2_33
BM39 U31 CC50
VCCIN_35 VCCIN_100 VDD2_34
BN40 U33 CE40
VCCIN_36 VCCIN_101 VDD2_35
BP12 V23 CG40
VCCIN_37 VCCIN_102 VDD2_36
BP39 V25 CH39
VCCIN_38 VCCIN_103 VDD2_37
BR10 V27 CJ40
VCCIN_39 VCCIN_104 +VCCIN VDD2_38
BR40 V29 CL40
VCCIN_40 VCCIN_105 VDD2_39
BT12 V31 CN40
VCCIN_41 VCCIN_106 VDD2_40
BT39 V33 CP47
VCCIN_42 VCCIN_107 VDD2_41

2
BU10 W22 CR40
VCCIN_43 VCCIN_108 RC1204 VDD2_42
BU40 W24 D50
VCCIN_44 VCCIN_109 VDD2_43
BV12 W28 1/20W_100_1%_0201 E51
VCCIN_45 VCCIN_110 VDD2_44
BY12 W32 F49
VCCIN_46 VCCIN_111 VDD2_45
CA10 T51
VCCIN_47 VDD2_46

1
CB12 R38 VCCIN_SENSE T52
VCCIN_48 VCCIN_SENSE VSSIN_SENSE VCCIN_SENSE [56] VDD2_47
D24 R37 VSSIN_SENSE [56]
VCCIN_49 VSSIN_SENSE
D26
VCCIN_50 VR_SVID_DATA
C D29 M12 VR_SVID_DATA [56] @ TGLLAKE-U_BGA1449 C
VCCIN_51 VIDSOUT

2
D30 M11 VR_SVID_CLK
VCCIN_52 VIDSCK VR_SVID_ALERT# VR_SVID_CLK [56]
D33 P12 RC1205
VCCIN_53 VIDALERT# VR_SVID_ALERT# [56]
D35 1/20W_100_1%_0201
VCCIN_54
E24
VCCIN_55
E26
VCCIN_56

1
E27
VCCIN_57
E29
VCCIN_58
E30
VCCIN_59
E32
VCCIN_60
E33
VCCIN_61
G2
VCCIN_62
G24
VCCIN_63
G26
VCCIN_64
G30
VCCIN_65 +VCCST_CPU

@ TGLLAKE-U_BGA1449

1U_6.3V_M_X5R_0201
VCCST:

1U_6.3V_M_X5R_0201

CC1213
1

CC1212
1 1x1uF 0402 Close SOC
+VCCSTG_OUT_LGC +VCCSTG_TERM
1x0402 (holder）
+VCCSTG_OUT_R 2
+VCCSTG_OUT RC1206 1 2 0_5%_0603 @ 2 @
1U_6.3V_M_X5R_0201

1
CC1211

2
@

+VCCSTG_CPU
B B

VCCSTG:

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1x1uF 0402 Close SOC

CC1214

CC1215
1x0402 (holder）
2 2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 CPU_PWR1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+1.8VALW +1.8VALW_PCH

PJ1301
1 2
+VCCIN_AUX UC1N 1 2
JUMP_43X39
14 OF 21
+VCCPRIM_1P8
@
AB12 CY18
VCCIN_AUX_1 VCCPRIM_1P8_1
AC10 CY20
VCCIN_AUX_2 VCCPRIM_1P8_2
AE10 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3 +3VALW_PCH +VCCPDSW_3P3
AK2 CY26
VCCIN_AUX_4 VCCPRIM_1P8_4
AR10 DA18
+VCCIN_AUX VCCIN_AUX_5 VCCPRIM_1P8_5 4mA
AT12 DA20
D VCCIN_AUX_6 VCCPRIM_1P8_6 RC1302 1 @ 2 0_0402_5% D
AU10 DA22
VCCIN_AUX_7 VCCPRIM_1P8_7
VCCDSW_3P3:

1U_6.3V_M_X5R_0201
AW10 DA24
VCCIN_AUX_8 VCCPRIM_1P8_8
BV1 DA26 1 1x0402(holder） DE31
VCCIN_AUX_9 VCCPRIM_1P8_9
1

RC1318 1 2 0_0402_5%

CC1301
BV39 DC18 +3VALW
RC1304 VCCIN_AUX_10 VCCPRIM_1P8_10 @
BW40 DC20
100_0402_1% VCCIN_AUX_11 VCCPRIM_1P8_11
BY39 DC22
VCCIN_AUX_12 VCCPRIM_1P8_12 2
CC1 DC24
VCCIN_AUX_13 VCCPRIM_1P8_13 @
CD12 DC26
VCCIN_AUX_14 VCCPRIM_1P8_14
2

VCCIN_AUX_VCCSENSE CF10 DD20

55 VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCIN_AUX_15 VCCPRIM_1P8_15
55 VCCIN_AUX_VSSSENSE CG12 DD22
VCCIN_AUX_16 VCCPRIM_1P8_16
CH10 DV22
VCCIN_AUX_17 VCCPRIM_1P8_17
1

CJ1
RC1306 VCCIN_AUX_18 +3VALW_PCH +VCCPRIM_3P3
CJ12 DA35 +VCCPRIM_3P3
100_0402_1% VCCIN_AUX_19 VCCPRIM_3P3_1 202mA
CK10 DC28
VCCIN_AUX_20 VCCPRIM_3P3_2 RC1303 1 2 0_0402_5%
CL12 DC30
VCCIN_AUX_21 VCCPRIM_3P3_3
CM10
VCCIN_AUX_22 VCCPRIM_3P3_4
DD30 VCCPRIM_3P3:
2

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
CP1 @ 1 1 1x0402(holder） DG26
VCCIN_AUX_23

CC1302

CC1303
CP10 DV34 +VCCRTCEXT 1x0402(holder） DF23
VCCIN_AUX_24 DCPRTC
CR12
VCCIN_AUX_25
CT10 DV46 +VCCLDOSTD_OUT_0P85
VCCIN_AUX_26 VCCLDOSTD_0P85 2 2
CU12
VCCIN_AUX_27 0.165A @ @
CY1 DV16 +VCCA_CLKLDO_1P8
VCCIN_AUX_28 VCCA_CLKLDO_1P8_1
AK1 DC15
VCCIN_AUX_29 VCCA_CLKLDO_1P8_2
VCCIN_AUX_VSSSENSE AV9 DV28
VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCDPHY_1P24 +VCCDPHY_1P24
AT9
VCCIN_AUX_VCCSENSE
DD38 +VCCDSW_1P05
1.05V / 0.76V VCCDSW_1P05
+VNN_BYPASS DD17
VCC_VNNEXT_1P05_1 FET TO VCCST_CPU
DD18 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1 & VCCSTG_CPU
BR4
1.05V 0.2ADA15 VCC1P05_OUT_FET_2
+V1.05A_BYPASS BT5 +VCC1.05_OUT_FET
VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
DA17
VCC_V1P05EXT_1P05_2
DA31
GPPC_B2_VRALERT_NDB39 VCCPRIM1P05_OUT_PCH_1 INTERNAL RAIL.
DC33
GPP_B2/VRALERT# VCCPRIM1P05_OUT_PCH_2 +VCC1.05_OUT_PCH
DV12 DC31 +VCC1.05_OUT_PCH
GPP_F22/VNN_CTRL VCCPRIM1P05_OUT_PCH_3 SHORT TO CPU SIDE VCCPLL.
DT12
GPP_F23/V1P05_CTRL
DC35 VCCRTC
VCCIN_AUX_VID0 VCCRTC
C
[55,46] VCCIN_AUX_VID0 DB37 DD37 +VCCPDSW_3P3 C
VCCIN_AUX_VID1 GPP_B0/CORE_VID0 VCCDSW_3P3
[55,46] VCCIN_AUX_VID1 DB38 DA28 +VCCPGPPR_3P3_1P8
GPP_B1/CORE_VID1 VCCPGPPR
CY31 VCCPRIM_1P05 is internal supply rail.
VCCPRIM_3P3_5 +VCCPRIM_3P3 Do not connect to external supply
CY33
VCCPRIM_3P3_6 Merge the pins together.
CV39 +VCCPRIM_1P8
VCCPRIM_1P8_18
AP12
RSVD_1

@ TGLLAKE-U_BGA1449
VID[1]VID[0] VCCIN_AUX
0 0 0
0 1 1.1
1 0 1.65
1 1 1.8

+1.8VALW_PCH
+VCCPRIM_1P8
+3VALW_PCH PJ1308 1.3A
1 2
1 2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
JUMP_43X39
RC1312
@ 1 1 1 VCCPRIM_1P8:

CC1308

CC1309

CC1310
20K_0201_5% 1x0402(holder） DG20
DC1301
2 2 2

2
2 1 GPPC_B2_VRALERT_N
6,44,55 H_PROCHOT#
2 1 @ @ @
RB521CM-30T2R_VMN2M-2

RC1314 1 @ 2 0_0402_5%

B B
+1.8VALW_PCH +VCCPGPPR_3P3_1P8

5mA
RC1307 1 2 0_0402_5% @
+VCCRTCEXT VCCPGPPR:Audio Power:

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1
0.1U_0402_10V7K

CC1306

CC1307
PDG: VCCRTCEXT
1 0.1u_0402 *1
CC1318

Place on Primary/Secondary Side 2 2

as close as possible to the package @ @
2 edge (less than 3mm).

VCCRTC +VCCDSW_1P05 +VCCDPHY_1P24 +VCCLDOSTD_OUT_0P85 +V1.05A_BYPASS +VNN_BYPASS +VCCPRIM_1P8 +VCCA_CLKLDO_1P8

RC1310 0.165A
1 2 VCCA_CLKLDO_1P8:
1

By Default: 47uF 0603 is stuffed

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

100K_0201_5%

1K_0402_5%

1 1 1 1 1 with a 0 Ohm resistor; Inductor is

CC1316

CC1317

CC1312

CC1313
4.7U_0402_6.3V6M

CC1311
2.2U_0402_6.3V6M

RC1309

RC1311

0_0805_5% @
placeholder; 100mOhm Resistor is

0_0402_5%
stuffed only when Inductor is

RC1313
stuffed.
2 2 2 2 2 @ Place the component near to package
2

@ pin
@ DW15 right after signal breakout.

2
It is recommended to have GND
shield around the VCC trace

47U_6.3V_M_X5R_0805_H1.25

1U_6.3V_M_X5R_0201
1 1 routing, and minimum of 4nH of loop

CC1314

CC1315
inductance from BGA to LC filter

2 2

A VCCRTC: VCCDSW_1P05: VCCDSW_1P05: VCCLDOSTD_0P85 For volume segment platform this rail is disabled. @ A
Keep the pin floating (do not short this pin to
1x0.1uF 0402 DG33 1x1uF 0402 DD34 1x4.7uF 0402 1x2.2uF 0402 ground).
1x1uF 0402 edge w/i3 mm edge w/i 3 mm

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 CPU PWR2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentName
Name Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

VDDQ_CPU :
+1.2V
PDG:1 , 2x47uF 0603, 8x10uF 0402, 8x1uF 0402,
vs
C750 ITL: 6x10uF 0402, 3x1uF 0402,10x1uF 0201,Reserve 8x10uF 0402,7x1uF 0201
S550 ITL 6x10uF 0402, 9x1uF 0201 Reserve 11x10uF 0402, 7x1uF 0201

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1
VDDQ:
CC1414

CC1405

CC1415

CC1406
D D
6x1uF 0402 Back ,Outer row
2 2 2 2 2x10uF 0402 back Outer row
3x0402 (holder） back Outer row
2x22uF 0603 (SODIMM need)
1x0603(holder)
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1 1 1 1 1
CC1402

CC1401

CC1413

CC1418

CC1419

CC1404

CC1421

CC1422

CC1403

CC1420

CC1416

CC1417

CC1423
2 2 2 2 2 2 2 2 2 2 2 2 2

@ @ @ @ @ @ @ @ @ @ @
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

C 1 1 1 1 1 1 1 C
CC1432

CC1434

CC1409

CC1424

CC1411

CC1407

CC1425

2 2 2 2 2 2 2
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1 1 1 1 1 1 1
CC1426

CC1428

CC1429

CC1430

CC1410

CC1408

CC1433

CC1412

CC1431

2 2 2 2 2 2 2 2 2

@ @ @ @ @ @ @

B B

+1.8VALW_PCH
+3VALW_PCH
+VCCIN +VCCIN_AUX +VCCIN_AUX

1 1 1
CC1441 EMC_NS@
12P_50V_F_COG_0402

CC1442 EMC_NS@
12P_50V_F_COG_0402

CC1443 EMC_NS@
12P_50V_F_COG_0402

56P_50V_J_NPO_0402
0.1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1

56P_50V_J_NPO_0402
CC1435 EMC_NS@
100P_0402_50V8J

CC1436 EMC_NS@
12P_50V_F_COG_0402

CC1437

CC1438 EMC_NS@
100P_0402_50V8J

CC1439 EMC_NS@
12P_50V_F_COG_0402

2 2 2 CC1447

CC1448
EMC@

EMC@
2 2 2 2 2 2 2
EMC_NS@

EMC CAPS refer CRB EMC CAPS refer CRB EMC Request 0810

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 PCH PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

UC1R
D UC1P D
UC1Q 18 OF 21
16 OF 21 17 OF 21
DP53 K34
A27 B19 BY44 CY44 DR11 VSS_2 VSS_46 K48
VSS_223 VSS_289 BY45 VSS_109 VSS_169 CY45 DR16 VSS_3 VSS_47 K5
A32 B2
VSS_224 VSS_290 BY47 VSS_110 VSS_170 CY47 DR22 VSS_4 VSS_48 L22
A45 B23
VSS_225 VSS_291 BY49 VSS_111 VSS_171 CY5 DR28 VSS_5 VSS_49 L28
A49 B27
VSS_226 VSS_292 BY9 VSS_112 VSS_172 D27 DR34 VSS_6 VSS_50 L34
AA41 B32
VSS_227 VSS_293 C13 VSS_113 VSS_173 D32 DR40 VSS_7 VSS_51 L39
AA48 B36
VSS_228 VSS_294 C19 VSS_114 VSS_174 D36 DR46 VSS_8 VSS_52 L41
AB5 B39
VSS_229 VSS_295 C23 VSS_115 VSS_175 D42 DT4 VSS_9 VSS_53 L42
AB7 B42
VSS_230 VSS_296 CA48 VSS_116 VSS_176 D49 DT50 VSS_10 VSS_54 L44
AB8 B48
VSS_231 VSS_297 CB41 VSS_117 VSS_177 D5 DU11 VSS_11 VSS_55 L45
AC44 B52
VSS_232 VSS_298 CC10 VSS_118 VSS_178 DA30 DU16 VSS_12 VSS_56 L47
AC49 B8
VSS_233 VSS_299 CC3 VSS_119 VSS_179 DA33 DU22 VSS_13 VSS_57 L49
AD4 BA48
VSS_234 VSS_300 CC5 VSS_120 VSS_180 DA53 DU28 VSS_14 VSS_58 M1
AD48 BA53
VSS_235 VSS_301 CD44 VSS_121 VSS_181 DC17 DU34 VSS_15 VSS_59 M2
AD8 BB4
VSS_236 VSS_302 CD48 VSS_122 VSS_182 DD15 DU40 VSS_16 VSS_60 M50
AF4 BB8
VSS_237 VSS_303 CD7 VSS_123 VSS_183 DD24 DU46 VSS_17 VSS_61 N22
AF8 BC1
VSS_238 VSS_304 CE49 VSS_124 VSS_184 DD26 DV1 VSS_18 VSS_62 N28
AG41 BC2
VSS_239 VSS_305 CG48 VSS_125 VSS_185 DD28 DV40 VSS_19 VSS_63 N34
AG42 BD12
VSS_240 VSS_306 CG51 VSS_126 VSS_186 DD31 DV52 VSS_20 VSS_64 N39
AG44 BD4
VSS_241 VSS_307 CG52 VSS_127 VSS_187 DD33 DW51 VSS_21 VSS_65 N41
AG45 BD48
VSS_242 VSS_308 CG9 VSS_128 VSS_188 DD35 E13 VSS_22 VSS_66 N48
AG47 BD8
VSS_243 VSS_309 CH41 VSS_129 VSS_189 DD39 E19 VSS_23 VSS_67 P11
AG48 BF39
VSS_244 VSS_310 CH42 VSS_130 VSS_190 DD45 E35 VSS_24 VSS_68 P14
AG53 BF4
VSS_245 VSS_311 CH44 VSS_131 VSS_191 DD51 E48 VSS_25 VSS_69 P16
AH4 BF41
VSS_246 VSS_312 CH45 VSS_132 VSS_192 DD52 G22 VSS_26 VSS_70 P18
AH8 BF42
VSS_247 VSS_313 CH47 VSS_133 VSS_193 DE3 G28 VSS_27 VSS_71 P20
AK12 BF44
VSS_248 VSS_314 CJ3 VSS_134 VSS_194 DE5 G34 VSS_28 VSS_72 P22
AK4 BF45
VSS_249 VSS_315 CJ5 VSS_135 VSS_195 DF19 G39 VSS_29 VSS_73 P33
AK48 BF47
VSS_250 VSS_316 CJ9 VSS_136 VSS_196 DF37 G48 VSS_30 VSS_74 P35
AK5 BF5
VSS_251 VSS_317 CK39 VSS_137 VSS_197 DG15 G51 VSS_31 VSS_75 P4
AK7 BF7
VSS_252 VSS_318 CK48 VSS_138 VSS_198 DG21 G52 VSS_32 VSS_76 P49
AK8 BF8
VSS_253 VSS_319 CK53 VSS_139 VSS_199 DG27 H12 VSS_33 VSS_77 P8
AM1 BG48
VSS_254 VSS_320 CL9 VSS_140 VSS_200 DG33 H22 VSS_34 VSS_78 R39
AM2 BG53
VSS_255 VSS_321 CN12 VSS_141 VSS_201 DG39 H28 VSS_35 VSS_79 R44
C AM4 BH1 C
VSS_256 VSS_322 CN48 VSS_142 VSS_202 DG45 H34 VSS_36 VSS_80 T19
AM8 BH2
VSS_257 VSS_323 CN51 VSS_143 VSS_203 DG5 H8 VSS_37 VSS_81 T29
AN41 BH4
VSS_258 VSS_324 CN52 VSS_144 VSS_204 DG53 J39 VSS_38 VSS_82 T33
AN42 BH8
VSS_259 VSS_325 CN9 VSS_145 VSS_205 DG6 J49 VSS_39 VSS_83 T4
AN44 BK12
VSS_260 VSS_326 CP3 VSS_146 VSS_206 DJ1 K16 VSS_40 VSS_84 T48
AN45 BK4
VSS_261 VSS_327 CP41 VSS_147 VSS_207 DJ2 K18 VSS_41 VSS_85 T8
AN47 BK48
VSS_262 VSS_328 CP42 VSS_148 VSS_208 DJ4 K20 VSS_42 VSS_86 U19
AN48 BK8
VSS_263 VSS_329 CP44 VSS_149 VSS_209 DK51 K22 VSS_43 VSS_87 U25
AN53 BL49
VSS_264 VSS_330 CP45 VSS_150 VSS_210 DL3 K28 VSS_44 VSS_88 U39
AP4 BM1
VSS_265 VSS_331 CP5 VSS_151 VSS_211 DL5 VSS_45 VSS_89 U49
AP8 BM4
VSS_266 VSS_332 CR48 VSS_152 VSS_212 DM10 VSS_90 V19
AT4 BM41
VSS_267 VSS_333 CR53 VSS_153 VSS_213 DM15 VSS_91 V4
AT48 BM42
VSS_268 VSS_334 CR9 VSS_154 VSS_214 DM21 VSS_92 V8
AT51 BM44
VSS_269 VSS_335 CT5 VSS_155 VSS_215 DM27 VSS_93 W1
AT8 BM45
VSS_270 VSS_336 CU4 VSS_156 VSS_216 DM33 VSS_94 W16
AV12 BM47
VSS_271 VSS_337 CU9 VSS_157 VSS_217 DM39 VSS_95 W26
AV39 BM8
VSS_272 VSS_338 CV10 VSS_158 VSS_218 DM4 VSS_96 W30
AV4 BN48
VSS_273 VSS_339 CV48 VSS_159 VSS_219 DM45 VSS_97 W39
AV5 BP41
VSS_274 VSS_340 CV5 VSS_160 VSS_220 DN1 VSS_98 W41
AV7 BP49
VSS_275 VSS_341 CV51 VSS_161 VSS_221 DN2 VSS_99 W42
AV8 BP5
VSS_276 VSS_342 CV52 VSS_162 VSS_222 VSS_100 W44
AW1 BP50
VSS_277 VSS_343 CY17 VSS_163 VSS_101 W45
AW2 BP7
VSS_278 VSS_344 CY22 VSS_164 VSS_102 W47
AW48 BT44
VSS_279 VSS_345 CY35 VSS_165 VSS_103 W48
AY4 BT48
VSS_280 VSS_346 CY41 VSS_166 VSS_104 Y4
AY41 BU49
VSS_281 VSS_347 CY42 VSS_167 VSS_105 Y49
AY42 BV3
VSS_282 VSS_348 VSS_168 VSS_106 Y50
AY44 BV48
VSS_283 VSS_349 VSS_107 Y8
AY45 BV5
VSS_284 VSS_350 VSS_108
AY47 BW10 TGLLAKE-U_BGA1449
VSS_285 VSS_351
AY8 BY41 @
VSS_286 VSS_352
AY9 BY42 TGLLAKE-U_BGA1449
VSS_287 VSS_353
B13 @
VSS_288

@
TGLLAKE-U_BGA1449
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 MCP(VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCIO_OUT

UC1S

2 RC212

2 RC213

2 RC214

2 RC219

2 RC218

2 RC215

2 RC216

2 RC217

2 RC220
19 OF 21

D D
DF53 C53
RSVD_19 RSVD_23
T35
RSVD_24
DF52 E53
@ RSVD_20 RSVD_25
CF39
RSVD_26
DT52 U35
PCH_IST_TP_1 RSVD_27
DU53 F53
PCH_IST_TP_0 RSVD_28

1
B53
RSVD_29
DF50 AP9

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%
RSVD_21 RSVD_30
DF49 A52
RSVD_22 RSVD_31
CY30 BF12
RSVD_TP_25 RSVD_TP_28
CY15 V21
RSVD_TP_26 RSVD_TP_29
W20
RSVD_TP_30
D4 U37
CPU_CFG14 RSVD_TP_27 RSVD_TP_31
CD39
CPU_CFG11 RSVD_TP_32
A6 U21
CPU_CFG10 IST_TP_1 RSVD_TP_33
A4 CB39
CPU_CFG9 IST_TP_0 RSVD_32
BB12
CPU_CFG7 RSVD_TP_34
W37
CPU_CFG4 RSVD_TP_35
AY12
CPU_CFG3 RSVD_TP_36
W38
CPU_CFG2 RSVD_TP_37
U38
CPU_CFG1 RSVD_TP_38
CY28
RSVD_TP_39
2 RC222

2 RC223

2 RC224

2 RC229

2 RC228

2 RC225

2 RC226

2 RC227

2 RC230
@ TGLLAKE-U_BGA1449

@ @ @ @ @ @ @ @
1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1

1K_0201_5% 1
C C

UC1T
20 OF 21

T15 A51
CPU_CFG14 V17 CFG_15 RSVD_TP_7 B51
U15 CFG_14 RSVD_TP_8
K11 CFG_13 C1
CPU_CFG11 K12 CFG_12 RSVD_TP_9 D2
CPU_CFG10 K9 CFG_11 RSVD_TP_10
CPU_CFG9 T17 CFG_10 CP39
K7 CFG_9 RSVD_TP_11 CU40
CPU_CFG7 H7 CFG_8 RSVD_TP_12 AK9
K8 CFG_7 RSVD_12
************************************** CFG_6
Change CFG Follow PDG_V1.0---Xukun1220 H9 AH9
CPU_CFG4 E6 CFG_5 RSVD_13
************************************** CPU_CFG3 CFG_4
H5 DW6
CPU_CFG2 E9 CFG_3 RSVD_14 DV6
CPU_CFG1 D9 CFG_2 RSVD_15
Pin Name Strap Description Configuration Default Value CFG_1
E7 DV4
CFG_0 RSVD_TP_13 DW3
RC1603 2 1 1/20W_49.9_1%_0201 B5 RSVD_TP_14
CFG[0] RSVD None CFG_RCOMP DU1
U17 RSVD_TP_15 DT2
H11 CFG_17 RSVD_TP_16
CFG[3:1] RSVD Pull-up to VCCIO 1Kohm CFG_16 DW2
Y1 RSVD_TP_17 DV2
M4 BPM#_3 RSVD_TP_18
eDP enable strap Pull-up to VCCIO / Pull-down BPM#_2
CFG[4] 1 = Disabled Platform design dependent 1Kohm AB4 E1
B
Y2 BPM#_1 RSVD_TP_19 F1 B
0 = Enabled BPM#_0 RSVD_TP_20
A3 AB2
B3 RSVD_6 RSVD_16
CFG[6:5] RSVD None RSVD_7 DR1
RC1604 1 2 2.2K_0402_1% AR2 RSVD_TP_21 DR2
AL10 TCP0_MBIAS_RCOMP RSVD_TP_22
PEG deferred link training Pull-up to VCCIO / Pull-down RSVD_TP_2
CFG[7] 1 = (default) PEG Trainimmediately Platform design dependent 1Kohm AM12 DR53
AH12 RSVD_TP_3 RSVD_TP_23 DW5
following RESET# de-assertion. RSVD_TP_4 RSVD_TP_24
AJ10
0 = PEG Wait for BIOS for training. AR1 RSVD_TP_5 DV51
RSVD_TP_6 VSS_1 DW52
BN10 TP_3 DV53
CFG[8] RSVD None RSVD_8 TP_4
BM12 W34
DD13 RSVD_9 RSVD_17 V35
DF13 RSVD_10 RSVD_18
CFG[11:9] RSVD Pull-up to VCCIO 1Kohm RSVD_11 D52
SKTOCC#
CFG[13:12] RSVD None
TGLLAKE-U_BGA1449
PEG60 Lane Reversal Pull-up to VCCIO / Pull-down @
CFG[14] 1 = Normal(Default) Platform design dependent 1Kohm
0 = Reversed

CFG[17:15] RSVD None

CPU PCIe Gen4 Bifurcation and Lane Reversal Mapping

CFG Signals Lanes

A
Bifurcation A

CFG [14] 0 1 2 3
1x4 1 0 1 2 3
1x4(Reversed) 0 3 2 1 0
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 DEBUG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

+0.6VS +1.2V

DDR4 Memory Down DDRB_BG1_R

DDP@
2 0_0201_5% DDRB_BG1

1
RD1701 1 DDRB_BG1 5 2
RD1702 CD1701

1
0_0402_5% .01U_0402_16V7-K
RD1765 @ MD@
0_0201_5% 1

2
SDP@
RPD23

2
DDRB_CLK0 1 4
UD1701 UD1702 DDRB_CLK0# 2 3
DDRB_MA0 P3 G2 DDRB_DQ16 DDRB_MA0 P3 G2 DDRB_DQ56 1/16W_36_5%_4P2R_0404
5 DDRB_MA0 DDRB_MA1 A0 DQL0 DDRB_DQ23 DDRB_MA1 A0 DQL0 DDRB_DQ58 +0.6VS
P7 F7 P7 F7 MD@
5 DDRB_MA1 DDRB_MA2 A1 DQL1 DDRB_DQ18 DDRB_MA2 A1 DQL1 DDRB_DQ63
R3 H3 R3 H3
5 DDRB_MA2 DDRB_MA3 A2 DQL2 DDRB_DQ17 DDRB_MA3 A2 DQL2 DDRB_DQ62
N7 H7 N7 H7 RPD24
5 DDRB_MA3 DDRB_MA4 A3 DQL3 DDRB_DQ22 DDRB_MA4 A3 DQL3 DDRB_DQ57 DDRB_MA14_WE#
N3 H2 N3 H2 1 4
5 DDRB_MA4 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ21 Byte 2 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ59 Byte 7 UD1_DDRB_UZQ RD1706 1 SDP@ 2 0_0402_5% DDRB_CKE0 2 3
5 DDRB_MA5 DDRB_MA6 A5 DQL5 DDRB_DQ20 DDRB_MA6 A5 DQL5 DDRB_DQ60
P2 J3 P2 J3 MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_MA6 DDRB_MA7 A6 DQL6 DDRB_DQ19 DDRB_MA7 A6 DQL6 DDRB_DQ61
D R8 J7 R8 J7 RD1709 1 DDP@ 2 240_0402_1% RPD25 D
5 DDRB_MA7 DDRB_MA8 A7 DQL7 DDRB_DQ2 DDRB_MA8 A7 DQL7 DDRB_DQ40 DDRB_MA6
R2 A3 R2 A3 1 4
5 DDRB_MA8 DDRB_MA9 A8 DQU0 DDRB_DQ5 DDRB_MA9 A8 DQU0 DDRB_DQ46 DDRB_BS0#
R7 B8 R7 B8 2 3
5 DDRB_MA9 DDRB_MA10 A9 DQU1 DDRB_DQ3 DDRB_MA10 A9 DQU1 DDRB_DQ42 UD2_DDRB_UZQ
M3 C3 M3 C3 RD1711 1 SDP@ 2 0_0402_5% MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_MA10 DDRB_MA11 A10/AP DQU2 DDRB_DQ6 DDRB_MA11 A10/AP DQU2 DDRB_DQ44
T2 C7 T2 C7
5 DDRB_MA11 DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ0 Byte 0 DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ41 Byte 5 RD1712 1 DDP@ 2 240_0402_1% RPD26
5 DDRB_MA12 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ4 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ47 DDRB_MA8 1 4
5 DDRB_MA13 A13 DQU5 DDRB_DQ1 A13 DQU5 DDRB_DQ43 DDRB_MA11
D3 D3 2 3
DDRB_MA14_WE# L2 DQU6 D7 DDRB_DQ7 DDRB_MA14_WE# L2 DQU6 D7 DDRB_DQ45 UD3_DDRB_UZQ RD1715 1 SDP@ 2 0_0402_5% MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_MA14_WE# DDRB_MA15_CAS# WE_N/A14 DQU7 DDRB_MA15_CAS# WE_N/A14 DQU7
M8 M8 RPD27
5 DDRB_MA15_CAS# DDRB_MA16_RAS# CAS_N/A15 +1.2V DDRB_MA16_RAS# CAS_N/A15 +1.2V DDRB_MA2
L8 L8 RD1718 1 DDP@ 2 240_0402_1% 1 4
5 DDRB_MA16_RAS# RAS_N/A16 D1 RAS_N/A16 D1 DDRB_PAR 2 3
DDRB_CLK0# K8 VDD1 J1 DDRB_CLK0# K8 VDD1 J1 MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_CLK0# DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0 K7 CK_C VDD2 L1 UD4_DDRB_UZQ RD1721 1 SDP@ 2 0_0402_5%
5 DDRB_CLK0 CK_T VDD3 R1 CK_T VDD3 R1 RPD28
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 RD1724 1 DDP@ 2 240_0402_1% DDRB_BG0 1 4
5 DDRB_CKE0 CKE VDD5 CKE VDD5 DDRB_MA0
G7 G7 2 3
DDRB_DQS#2 F3 VDD6 B9 DDRB_DQS#7 F3 VDD6 B9 MD@ 1/16W_36_5%_4P2R_0404
DDRB_DQS2 G3 DQSL_C VDD7 J9 DDRB_DQ[0..63] DDRB_DQS7 G3 DQSL_C VDD7 J9
DDRB_DQ[0..63] 5 RPD29
DDRB_DQS#0 A7 DQSL_T VDD8 L9 DDRB_DQS#5 A7 DQSL_T VDD8 L9 DDRB_MA10 1 4
+1.2V DDRB_DQS0 B7 DQSU_C VDD9 T9 DDRB_DQS#[0..7] +1.2V DDRB_DQS5 B7 DQSU_C VDD9 T9 DDRB_MA4 2 3
DQSU_T VDD10 DDRB_DQS#[0..7] 5 DQSU_T VDD10 MD@ 1/16W_36_5%_4P2R_0404
2 0_0402_5% @ DDRB_DM1 DDRB_DQS[0..7] 2 0_0402_5% @ DDRB_DM2 +1.2V
RD1732 1 E2 A1 RD1733 1 E2 A1 RPD30
NF/UDM_N/UDBI_N VDDQ1 DDRB_DQS[0..7] 5 NF/UDM_N/UDBI_N VDDQ1
RD1735 1 2 0_0402_5% @ DDRB_DM0 E7 C1 RD1736 1 2 0_0402_5% @ DDRB_DM3 E7 C1 DDRB_MA3 1 4
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_ACT# 2 3
DDRB_BS0# N2 VDDQ3 F2 DDRB_BS0# N2 VDDQ3 F2 MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_BS0# DDRB_BS1# BA0 VDDQ4 DDRB_BS1# BA0 VDDQ4
5 DDRB_BS1#
N8 J2 N8 J2 1 RPD31
BA1 VDDQ5 BA1 VDDQ5 DDRB_MA9

1
F8 F8 CD1702 1 4
DDRB_ACT# L3 VDDQ6 J8 DDRB_ACT# L3 VDDQ6 J8 0.1U_6.3V_K_X5R_0201 RD1743 DDRB_MA1 2 3
5 DDRB_ACT# DDRB_CS0# ACT_N VDDQ7 DDRB_CS0# ACT_N VDDQ7
L7 A9 L7 A9 1.8K_0402_1% MD@ 1/16W_36_5%_4P2R_0404
5 DDRB_CS0# DDRB_ALERT# CS_N VDDQ8 DDRB_ALERT# CS_N VDDQ8 MD@ 2
P9 D9 P9 D9 MD@ RPD32
5 DDRB_ALERT# ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 DDRB_MA7
+2.5V_DDR 1 4
DDRB_BG0 VDDQ10 DDRB_BG0 VDDQ10

2
M2 M2 DDRB_MA13 2 3
5 DDRB_BG0 BG0 BG0
B1 B1 MD@ 1/16W_36_5%_4P2R_0404
DDRB_ODT0 K3 VPP1 R9 DDRB_ODT0 K3 VPP1 R9 1 RD1748 2 MD@ +VREF_CA_MD
5 DDRB_ODT0 5 DDR_SB_VREFCA RPD33
ODT VPP2 ODT VPP2 DDRB_MA12 1 4

CD1703
1U_6.3V_M_X5R_0201

CD1704
1U_6.3V_M_X5R_0201
2.7_0402_1%
DDRB_PAR T3 M1 +VREF_CA_MD DDRB_PAR T3 M1 +VREF_CA_MD DDRB_MA5 2 3

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
5 DDRB_PAR PAR VREFCA 1 1 PAR VREFCA 1

1
CD1707

CD1709
1 MD@ 1/16W_36_5%_4P2R_0404
RD1745 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 RD1747 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1 1 1

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201
1 1 CD1711 CD1712

CD1710
TEN VSS1 K1 TEN VSS1 K1 RD1749 0.1U_6.3V_K_X5R_0201

CD1705 MD@

CD1706

CD1708
1 1 0.022U_16V_K_X7R_0402 RPD34
CPU_DRAMRST# VSS2 2 2 CPU_DRAMRST# VSS2 2 1.8K_0402_1% DDRB_MA16_RAS#
P1 N1 P1 N1 MD@ 1 4

MD@

MD@
5,18 CPU_DRAMRST# RESET_N VSS3 T1 RESET_N VSS3 T1 MD@ 2 @ DDRB_BS1# 2 3
VSS4 VSS4 2 2
2 2

2
1
F1 B2 F1 B2 MD@ 1/16W_36_5%_4P2R_0404
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 RD1752

MD@
24.9_0402_1% RPD35
A2 VSSQ2 VSS6 K9 @ A2 VSSQ2 VSS6 K9 DDRB_MA15_CAS# 1 4

MD@
@ @
C VSSQ3 VSS8 VSSQ3 VSS8 MD@ DDRB_CS0# C
D2 D2 2 3
E3 VSSQ4 T7 1 DDP@ 2 E3 VSSQ4 T7 1 DDP@ 2 MD@ 1/16W_36_5%_4P2R_0404
VSSQ5 VSS7 VSSQ5 VSS7

2
A8 RD1750 0_0402_5% A8 RD1751 0_0402_5%
D8 VSSQ6 D8 VSSQ6
E8 VSSQ7 M9 DDRB_BG1_R E8 VSSQ7 M9 DDRB_BG1_R DDRB_BG1_R RD1739 2 DDP@ 1 1/20W_36_5%_0201
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9 DDRB_ODT0 RD1708 2 MD@ 1 1/20W_36_5%_0201
H9 VSSQ9 E9 UD1_DDRB_UZQ H9 VSSQ9 E9 UD2_DDRB_UZQ
VSSQ10 VSS10 VSSQ10 VSS10 VDDQ: +1.2V
F9 F9 16x1uF 4 per DRAM
ZQ ZQ
+1.2V 5x10uF distribute evenly across dram DDRB_ALERT#
1

1
RD1746 1 MD@ 2 49.9_0402_1%
RD1753 RD1754
K4AAG165WA-BCWE_FBGA96 240_0402_1% K4AAG165WA-BCWE_FBGA96 240_0402_1%
MD@ MD@ First DRAM 1x10uF 4x1uF 2nd DRAM 1x10uF 4x1uF
@ @
2

CD1729
4.3U_0402_4V6-M

CD1723
1U_6.3V_M_X5R_0201

CD1724
1U_6.3V_M_X5R_0201

CD1719
1U_6.3V_M_X5R_0201

CD1713
1U_6.3V_M_X5R_0201

CD1732
10U 6.3V M X5R 0402

CD1731
4.3U_0402_4V6-M

CD1715
1U_6.3V_M_X5R_0201

CD1716
1U_6.3V_M_X5R_0201

CD1717
1U_6.3V_M_X5R_0201

CD1728
1U_6.3V_M_X5R_0201

CD1733
10U 6.3V M X5R 0402

CD1742
22P_0402_50V8-J
1 1 1 1 1 1 1 1 1 1 1

3
2

4
2 2 2 2 2

4
2 2 2 2 2 2@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@

MD_3T@

MD_N3T@

MD_N3T@

MD@
UD1703
UD1704
DDRB_MA0 P3 G2 DDRB_DQ48
DDRB_MA1 P7 A0 DQL0 F7 DDRB_DQ51 DDRB_MA0 P3 G2 DDRB_DQ8
DDRB_MA2 R3 A1 DQL1 H3 DDRB_DQ52 DDRB_MA1 P7 A0 DQL0 F7 DDRB_DQ12
DDRB_MA3 N7 A2 DQL2 H7 DDRB_DQ55 DDRB_MA2 R3 A1 DQL1 H3 DDRB_DQ11
DDRB_MA4 A3 DQL3 DDRB_DQ50 DDRB_MA3 A2 DQL2 DDRB_DQ14
UD1701 UD1704
N3 H2 N7 H7
DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ54 Byte 6 DDRB_MA4 N3 A3 DQL3 H2 DDRB_DQ10
DDRB_MA6 P2 A5 DQL5 J3 DDRB_DQ53 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ13 Byte 1 3rd DRAM 1x10uF 4x1uF 4th DRAM 2x10uF 4x1uF
DDRB_MA7 R8 A6 DQL6 J7 DDRB_DQ49 DDRB_MA6 P2 A5 DQL5 J3 DDRB_DQ9
DDRB_MA8 R2 A7 DQL7 A3 DDRB_DQ33 DDRB_MA7 R8 A6 DQL6 J7 DDRB_DQ15
DDRB_MA9 R7 A8 DQU0 B8 DDRB_DQ38 DDRB_MA8 R2 A7 DQL7 A3 DDRB_DQ28
DDRB_MA10 M3 A9 DQU1 C3 DDRB_DQ32 DDRB_MA9 R7 A8 DQU0 B8 DDRB_DQ30

CD1721
1U_6.3V_M_X5R_0201

CD1725
1U_6.3V_M_X5R_0201

CD1722
1U_6.3V_M_X5R_0201

CD1718
1U_6.3V_M_X5R_0201

CD1734
10U 6.3V M X5R 0402

CD1730
4.3U_0402_4V6-M

1U_6.3V_M_X5R_0201

CD1727
1U_6.3V_M_X5R_0201

CD1726
1U_6.3V_M_X5R_0201

CD1714
1U_6.3V_M_X5R_0201

CD1735
10U 6.3V M X5R 0402

CD1736
10U 6.3V M X5R 0402

CD1741
22P_0402_50V8-J
DDRB_MA11 T2 A10/AP DQU2 C7 DDRB_DQ37 DDRB_MA10 M3 A9 DQU1 C3 DDRB_DQ25

CD1720 @
DDRB_MA12 A11 DQU3 DDRB_DQ34 Byte 4 DDRB_MA11 A10/AP DQU2 DDRB_DQ26 1 1 1 1 1 1 1 1 1 1 1 1

3
M7 C2 T2 C7
DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ39 DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ29 Byte 3
A13 DQU5 D3 DDRB_DQ35 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ31
DDRB_MA14_WE# DQU6 DDRB_DQ36 A13 DQU5 DDRB_DQ24 2 2 2 2 2@

4
L2 D7 D3 2 2 2 2 2 2 2

MD_N3T@

MD_N3T@

MD_3T@

MD_N3T@

MD_N3T@

MD@

MD@
DDRB_MA15_CAS# M8 WE_N/A14 DQU7 DDRB_MA14_WE# L2 DQU6 D7 DDRB_DQ27 @
DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DDRB_MA15_CAS# M8 WE_N/A14 DQU7
RAS_N/A16 D1 DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRB_CLK0# K8 VDD1 J1 RAS_N/A16 D1
B
DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0# K8 VDD1 J1 B
CK_T VDD3 R1 DDRB_CLK0 K7 CK_C VDD2 L1
DDRB_CKE0 VDD4 CK_T VDD3
UD1703 UD1702
K2 B3 R1
CKE VDD5 G7 DDRB_CKE0 K2 VDD4 B3
DDRB_DQS#6 F3 VDD6 B9 CKE VDD5 G7
DDRB_DQS6 G3 DQSL_C VDD7 J9 DDRB_DQS#1 F3 VDD6 B9
DDRB_DQS#4 A7 DQSL_T VDD8 L9 DDRB_DQS1 G3 DQSL_C VDD7 J9
+1.2V DDRB_DQS4 B7 DQSU_C VDD9 T9 DDRB_DQS#3 A7 DQSL_T VDD8 L9
DQSU_T VDD10 +1.2V DDRB_DQS3 B7 DQSU_C VDD9 T9
RD1755 1 2 0_0402_5% @ DDRB_DM4 E2 A1 DQSU_T VDD10
RD1756 1 2 0_0402_5% @ DDRB_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1757 1 2 0_0402_5% @ DDRB_DM6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD1758 1 2 0_0402_5% @ DDRB_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRB_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRB_BS1# N8 BA0 VDDQ4 J2 DDRB_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRB_BS1# N8 BA0 VDDQ4 J2
DDRB_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
ACT_N VDDQ7 VDDQ6 +2.5V_DDR
DDRB_CS0# L7 A9 DDRB_ACT# L3 J8
DDRB_ALERT# P9 CS_N VDDQ8 D9 DDRB_CS0# L7 ACT_N VDDQ7 A9
ALERT_N VDDQ9 G9 +2.5V_DDR DDRB_ALERT# P9 CS_N VDDQ8 D9
DDRB_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V_DDR
VPP:
M2 G9 8x1uF

CD1737
10U 6.3V M X5R 0402

CD1738
10U 6.3V M X5R 0402

CD1739
10U 6.3V M X5R 0402

CD1740
10U 6.3V M X5R 0402
BG0 B1 DDRB_BG0 M2 VDDQ10

CD1745
22P_0402_50V8-J

CD1746
22P_0402_50V8-J
DDRB_ODT0 K3 VPP1 R9 BG0 B1 3x10uF
ODT VPP2 DDRB_ODT0 VPP1 1 1 1 1 1 1
K3 R9
DDRB_PAR T3 M1 +VREF_CA_MD ODT VPP2
CD1747
1U_6.3V_M_X5R_0201

CD1749
1U_6.3V_M_X5R_0201

PAR VREFCA DDRB_PAR T3 M1 +VREF_CA_MD

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1

MD@

MD@

MD@

MD@
RD1759 1 MD@ 2 TEN_UD3 N9 E1 PAR VREFCA 2 2 2 2 2@ 2@
.047U_0402_16V7K

0.1U_6.3V_K_X5R_0201

CD1751 MD@

CD1752
10K_0402_5% 1 1
TEN VSS1 K1 RD1760 1 MD@ 2 10K_0402_5% TEN_UD4 N9 E1
CD1748 MD@

CD1750

CPU_DRAMRST# VSS2 1 1 TEN VSS1

P1 N1 K1

CD1753 MD@
.047U_0402_16V7K

CD1754
0.1U_6.3V_K_X5R_0201
RESET_N VSS3 2 2 CPU_DRAMRST# VSS2 1 1
T1 P1 N1
F1 VSS4 B2 RESET_N VSS3 T1 2 2
MD@

MD@

H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2 @

A2 VSSQ2 VSS6 K9 @ H1 VSSQ1 VSS5 G8 2 2
D2 VSSQ3 VSS8 A2 VSSQ2 VSS6 K9 @
E3 VSSQ4 T7 1 DDP@ 2 D2 VSSQ3 VSS8
A8 VSSQ5 VSS7 RD1761 0_0402_5% E3 VSSQ4 T7 1 DDP@ 2
D8 VSSQ6 A8 VSSQ5 VSS7 RD1762 0_0402_5% +0.6VS
E8 VSSQ7 M9 DDRB_BG1_R D8 VSSQ6
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DDRB_BG1_R
VSSQ9 UD3_DDRB_UZQ VSSQ8 VSS9 VTT:
H9 E9 C9 8x1uF
VSSQ10 VSS10 F9 H9 VSSQ9 E9 UD4_DDRB_UZQ

CD1743

CD1744

CD1755
1U_6.3V_M_X5R_0201

CD1756
1U_6.3V_M_X5R_0201

CD1757
1U_6.3V_M_X5R_0201

CD1758
1U_6.3V_M_X5R_0201

CD1759
1U_6.3V_M_X5R_0201

CD1760
1U_6.3V_M_X5R_0201

CD1761
1U_6.3V_M_X5R_0201

CD1762
1U_6.3V_M_X5R_0201

CD1764
10U 6.3V M X5R 0402

CD1763
10U 6.3V M X5R 0402

CD1765
22P_0402_50V8-J

CD1766
22P_0402_50V8-J
2x10uF

4.3U_0402_4V6-M

4.3U_0402_4V6-M
ZQ VSSQ10 VSS10 F9
ZQ 1 1 1 1 1 1 1 1 1 1 1 1
1

3
1

RD1763
K4AAG165WA-BCWE_FBGA96 240_0402_1% RD1764

4
MD@ 240_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2

MD_3T@

MD_3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD@
A @ K4AAG165WA-BCWE_FBGA96 A
MD@ @ @

MD@
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2017/06/24 Deciphered Date 2018/06/23 DDR4 Memory Down

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HS45A/HS55A 0.1

Date: Monday, November 02, 2020 Sheet 17 of 60

5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM +1.2V

1
+1.2V +1.2V
JDDR1B
RD1801
+1.2V JDDR1A +1.2V 240_0402_1%
@
DDRA_MA3 131 132 DDRA_MA2
A3 A2

2
1 2 DDRA_MA1 133 134 DDRA_EVENT#
DDRA_DQ59 3 VSS_1 VSS_2 4 DDRA_DQ58 135 A1 EVENT_n 136
5 DQ5 DQ4 6 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ60 VSS_3 VSS_4 DDRA_DQ62 5 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t DDRA_CLK1# DDRA_CLK1 5
7 8 139 140
DQ1 DQ0 DDRA_DQ[0..63] 5 DDRA_CLK0# CK0_c CK1_c DDRA_CLK1# 5
9 10 141 142
DDRA_DQS#7 VSS_5 VSS_6 DDRA_DQ[0..63] 5 DDRA_PAR VDD_11 VDD_12 DDRA_MA0
11 12 143 144
DDRA_DQS7 DQS0_C DM0_n/DBIO_n/NC DDRA_DQS#[0..7] 5 DDRA_PAR Parity A0
13 14
DQS0_t VSS_7 DDRA_DQ57 DDRA_DQS#[0..7] 5
15 16
D DDRA_DQ61 17 VSS_8 DQ6 18 DDRA_DQS[0..7] DDRA_BS1# 145 146 DDRA_MA10 D
DQ7 VSS_9 DDRA_DQ56 DDRA_DQS[0..7] 5 5 DDRA_BS1# BA1 A10/AP
19 20 147 148
DDRA_DQ63 21 VSS_10 DQ2 22 DDRA_MA[0..13] DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BS0#
DQ3 VSS_11 DDRA_DQ45 DDRA_MA[0..13] 5 5 DDRA_CS0# DDRA_MA14_WE# CS0_n BA0 DDRA_MA16_RAS# DDRA_BS0# 5
23 24 151 152
DDRA_DQ47 VSS_12 DQ12 5 DDRA_MA14_WE# WE_n/A14 RAS_n/A16 DDRA_MA16_RAS# 5
25 26 153 154
27 DQ13 VSS_13 28 DDRA_DQ44 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS#
DDRA_DQ46 VSS_14 DQ8 5 DDRA_ODT0 DDRA_CS1# ODT0 CAS_n/A15 DDRA_MA13 DDRA_MA15_CAS# 5
29 30 157 158
DQ9 VSS_15 DDRA_DQS#5 5 DDRA_CS1# CS1_n A13
31 32 159 160
33 VSS_16 DQS1_c 34 DDRA_DQS5 DDRA_ODT1 161 VDD_17 VDD_18 162
DM1_n/DBl1_n/NC DQS1_t 5 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMM
35 36 163 164
DDRA_DQ40 37 VSS_17 VSS_18 38 DDRA_DQ42 165 VDD_19 VREFCA 166 DDRA_SA2
39 DQ15 DQ14 40 167 C1/CS3_n/NC SA2 168

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
DDRA_DQ43 41 VSS_19 VSS_20 42 DDRA_DQ41 DDRA_DQ19 169 VSS_53 VSS_54 170 DDRA_DQ21

CD1801

CD1802
DQ10 DQ11 DQ37 DQ36 1 1
43 44 171 172
DDRA_DQ38 45 VSS_21 VSS_22 46 DDRA_DQ36 DDRA_DQ17 173 VSS_55 VSS_56 174 DDRA_DQ23
47 DQ21 DQ20 48 175 DQ33 DQ32 176
DDRA_DQ37 49 VSS_23 VSS_24 50 DDRA_DQ39 DDRA_DQS#2 177 VSS_57 VSS_58 178 2 2
51 DQ17 DQ16 52 DDRA_DQS2 179 DQS4_c DM4_n/DBl4_n/NC 180
DDRA_DQS#4 53 VSS_25 VSS_26 54 181 DQS4_t VSS_59 182 DDRA_DQ20 @
DDRA_DQS4 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRA_DQ22 183 VSS_60 DQ39 184
57 DQS2_t VSS_27 58 DDRA_DQ34 185 DQ38 VSS_61 186 DDRA_DQ16
DDRA_DQ35 59 VSS_28 DQ22 60 DDRA_DQ18 187 VSS_62 DQ35 188
61 DQ23 VSS_29 62 DDRA_DQ33 189 DQ34 VSS_63 190 DDRA_DQ12
DDRA_DQ32 63 VSS_30 DQ18 64 DDRA_DQ14 191 VSS_64 DQ45 192
65 DQ19 VSS_31 66 DDRA_DQ52 193 DQ44 VSS_65 194 DDRA_DQ13
DDRA_DQ51 67 VSS_32 DQ28 68 DDRA_DQ15 195 VSS_66 DQ41 196
69 DQ29 VSS_33 70 DDRA_DQ53 197 DQ40 VSS_67 198 DDRA_DQS#1
DDRA_DQ48 71 VSS_34 DQ24 72 199 VSS_68 DQS5_c 200 DDRA_DQS1
73 DQ25 VSS_35 74 DDRA_DQS#6 201 DM5_n/DBl5_n/NC DQS5_t 202
+1.2V 75 VSS_36 DQS3_c 76 DDRA_DQS6 DDRA_DQ8 203 VSS_69 VSS_70 204 DDRA_DQ10
77 DM3_n/DBl3_n/NC DQS3_t 78 205 DQ46 DQ47 206
DDRA_DQ54 79 VSS_37 VSS_38 80 DDRA_DQ50 DDRA_DQ9 207 VSS_71 VSS_72 208 DDRA_DQ11
81 DQ30 DQ31 82 209 DQ42 DQ43 210
DDRA_DQ55 83 VSS_39 VSS_40 84 DDRA_DQ49 DDRA_DQ5 211 VSS_73 VSS_74 212 DDRA_DQ7
DQ26 DQ27 DQ52 DQ53
1

85 86 213 214
RD1802 87 VSS_41 VSS_42 88 DDRA_DQ4 215 VSS_75 VSS_76 216 DDRA_DQ6
RD1803 CB5/NC CB4/NC DQ49 DQ48
89 90 217 218
240_0402_1% 240_0402_1% VSS_43 VSS_44 DDRA_DQS#0 VSS_77 VSS_78
C 91 92 219 220 C
93 CB1/NC CB0/NC 94 DDRA_DQS0 221 DQS6_c DM6_n/DBl6_n/NC 222
VSS_45 VSS_46 DQS6_t VSS_79
2

DDRA_DQS#8 95 96 223 224 DDRA_DQ1

DDRA_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRA_DQ3 225 VSS_80 DQ54 226
99 DQS8_t VSS_47 100 227 DQ55 VSS_81 228 DDRA_DQ2
101 VSS_48 CB6/NC 102 DDRA_DQ0 229 VSS_82 DQ50 230
103 CB2/NC VSS_49 104 231 DQ51 VSS_83 232 DDRA_DQ29
105 VSS_50 CB7/NC 106 DDRA_DQ27 233 VSS_84 DQ60 234
107 CB3/NC VSS_51 108 CPU_DRAMRST# 235 DQ61 VSS_85 236 DDRA_DQ31
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 CPU_DRAMRST# 5,17 DDRA_DQ24 VSS_86 DQ57
109 110 237 238

0.1U_6.3V_K_X5R_0201
5 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 5 DQ56 VSS_87 DDRA_DQS#3
111 112 239 240

CD1803
VDD_1 VDD_2 1 VSS_88 DQS7_c
DDRA_BG1 113 114 DDRA_ACT# 241 242 DDRA_DQS3
5 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 5 DM7_n/DBl7_n/NC DQS7_t
115 116 243 244
5 DDRA_BG0 BG0 ALERT_n DDRA_ALERT# 5 DDRA_DQ26 VSS_89 VSS_90 DDRA_DQ28
117 118 245 246
DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 2@ 247 DQ62 DQ63 248
DDRA_MA9 121 A12 A11 122 DDRA_MA7 DDRA_DQ25 249 VSS_91 VSS_92 250 DDRA_DQ30
123 A9 A7 124 251 DQ58 DQ59 252
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
DDRA_MA6 A8 A5 DDRA_MA4 7 SMB_CLK_S3 +VDD_SPD SCL SDA DDRA_SA0 SMB_DATA_S3 7
127 128 255 256
129 A6 A4 130 257 VDDSPD SA0 258
+0.6VS

2.2U_0402_6.3V6M
VDD_7 VDD_8 259 VPP_1 VTT 260 DDRA_SA1

0.1U_6.3V_K_X5R_0201
1 1 VPP_2 SA1

CD1804

CD1805
RD1804 1 @ 2 0_5%_0603 261 262
+3VS GND_1 GND_2
ARGOS_D4AR0-26001-1P40 2 2
ME@ ARGOS_D4AR0-26001-1P40
ME@

+2.5V_DDR RD1805 1 @ 2 0_5%_0603 +VPP VDDSPD:

+1.2V 1x2.2uF
0.1U_6.3V_K_X5R_0201

1x0.1uF
1
CD1806

RD1806
2 1K_0402_1%
B B
+2.5V_DDR
2

RD1807 1 2 2_0402_5% +VREF_CA_DIMM +1.2V 2nd DRAM 1x10uF 4x1uF

5 DDR_SA_VREFCA
VPP:

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1x1uF
0.1U_6.3V_K_X5R_0201

1
1

CD1815

CD1812

CD1811

CD1814

CD1813
1 1x10uF

0.1U_6.3V_K_X5R_0201
0.022U_16V_K_X7R_0402 RD1808 VDDQ:
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
CD1816

1 1 1 1

CD1836
1K_0402_1%
CD1818

CD1819

CD1820

CD1822

CD1823

CD1824

CD1817

CD1821

CD1833

CD1834

CD1835

CD1837
33P_0402_50V8J

CD1838
33P_0402_50V8J
2 8x1uF
2 8x10uF 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

2 2@ 2 2@
2

RD1809
24.9_0402_1%
2@ 2@ 2 2 2 2@ 2 2 2 2@ 2 2 2 2
@ @ @ @ @ @
2

+3VS +3VS +3VS

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1

CD1825

CD1826

CD1828

CD1829

CD1830

CD1832

CD1831

RD1810 RD1811 RD1812 CD1827 +0.6VS

1 1 1 1 1 1 1 1
0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
2@ 2 2 2 2 2 2 2
VTT:
2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DDRA_SA0 DDRA_SA1 DDRA_SA2
2x1uF
@ @

CD1809

CD1810

CD1807

CD1808
1x10uF
1 1 1 1
1

RD1813 RD1814 RD1815

2 2 2 2@
0_0402_5% 0_0402_5% 0_0402_5%
@
A @ @ @ A
2

SPD Address = A0
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

N16x GPIO

GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
GPIO0 OUT - GPU Core VDD PWM control signal
FBVDDQ Other
Min FBVDD (GPU+Mem) (1.05V)
GPIO1 OUT N/A FB Enable for GC6 2.0 GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
D GPIO2 OUT N/A D

N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
GPIO3 OUT N/A
N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

GPIO10 OUT FBVREF_ALTV for GDDR5

GPIO11 OUT - N16x Multi-level Straps

GPIO12 IN AC Power Detect Input (10K pull High)
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C C
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A

GPIO21 OUT GPU PCIe self-reset control

OVERT OUT Active Low Thermal Catastrophic Over Temperature

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON +3V_1.8VGS +3.3V_1.8V_AON

2
RV2001 RV2002 RV2003
0_0402_5% 10K_0402_5%
0_0402_5% +1.0VGS
@ OPT@
@
UV1A ? COMMON INS35853665

1
1/14 PCI_EXPRESS
CV2003 1 Under Near GPU and PS
D D
0.1U_6.3V_K_X5R_0201
@

CV2008
10U 6.3V M X5R 0402

CV2009 OPTN17@
10U 6.3V M X5R 0402

OPTN17@
CV2004 OPT@
1U_6.3V_M_X5R_0201

CV2005 OPTN17@
4.7U_0402_6.3V6M

CV2006 OPT@
4.7U_0402_6.3V6M

CV2007 OPTN17@
4.7U_0402_6.3V6M
2 2 2

22U_0603_6.3V6-M
2
AA22 1 1 1 1 PEX_DVDD
PLT_RST_VGA# AC7 PEX_DVDD_1 AB23
26 PLT_RST_VGA# PEX_DVDD_2 1 N16:+1.05VGS(recommend)
OPT@ QV2001 AC24
1 3 CLK_REQ_GPU# AC6 PEX_RST_N PEX_DVDD_3 AD25 1 1 +1.0VGS(Used)

OPTN17@
10 GPU_CLKREQ# PEX_CLKREQ_N PEX_DVDD_4 2 2 2 2 N17:+1.0VGS
AE26

CV2010
CLK_PCIE_GPU AE8 PEX_DVDD_5 AE27 2
10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK PEX_DVDD_6
LSI1012XT1G_SC-89-3 AD8
10 CLK_PCIE_GPU# PEX_REFCLK_N
RV2004 1 @ 2 0_0402_5% PCIE4_CRX_GTX_P0 OPT@ CV2001 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P0 AC9 PEX_HVDD +3V_1.8VGS
PCIE4_CRX_GTX_N0 OPT@ CV2011 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N0 AB9 PEX_TX0
PEX_TX0_N
2000mA

2
PCIE4_CTX_C_GRX_P0 AG6 Under GPU Near GPU GPU and PS OPTN17@
RV2005 PCIE4_CTX_C_GRX_N0 PEX_RX0 (below 150mils) PEX_HVDD
AG7 AA10 2 1 0_0805_5%
10K_0402_5% PEX_RX0_N PEX_HVDD_1 AA12
@ PCIE4_CRX_GTX_P1 PEX_HVDD_2 RV2006
OPT@ CV2012 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P1 AB10 AA13 +1.0VGS

CV2014 OPT@
1U_6.3V_M_X5R_0201

CV2015 OPTN17@
1U_6.3V_M_X5R_0201

CV2016
1U_6.3V_M_X5R_0201

CV2017
1U_6.3V_M_X5R_0201

CV2018 OPT@
4.7U_0402_6.3V6M

CV2019 OPTN17@
4.7U_0402_6.3V6M

CV2020 OPT@
10U 6.3V M X5R 0402

CV2021 OPTN17@
10U 6.3V M X5R 0402

CV2022 OPT@
22U_0603_6.3V6-M

CV2023 OPT_RF@
33P_0402_50V8J
PCIE4_CRX_GTX_N1 OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N1 AC10 PEX_TX1 PEX_HVDD_3 AA16 OPTN16@
1 PEX_TX1_N PEX_HVDD_4 1 1 1 1 1 1 2 2 1 1
AA18 2 1 0_0805_5%
PCIE4_CTX_C_GRX_P1 AF7 PEX_HVDD_5 AA19
PCIE4_CTX_C_GRX_N1 PEX_RX1 PEX_HVDD_6 RV2007
AE7 AA20
PEX_RX1_N PEX_HVDD_7 AA21 2 2 2 2 2 2 1 1 2 2
PCIE4_CRX_GTX_P2 OPT@ CV2002 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P2 AD11 PEX_HVDD_8 AB22 @ @ PEX_HVDD
PCIE4_CRX_GTX_N2 OPT@ CV2024 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N2 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
PCIE4_CTX_C_GRX_P2 AE9 PEX_HVDD_11 AE25
PEX_RX2 PEX_HVDD_12 N17:+1.8VGS
PCIE4_CTX_C_GRX_N2 AF9 AF26
PEX_RX2_N PEX_HVDD_13 AF27 For RF
PCIE4_CRX_GTX_P3 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P3 AC12 PEX_HVDD_14
PCIE4_CRX_GTX_N3 OPT@ CV2026 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N3 AB12 PEX_TX3
PEX_TX3_N Change by Bourne 20170412
PCIE4_CTX_C_GRX_P3 AG9
PCIE4_CTX_C_GRX_N3 AG10 PEX_RX3
PEX_RX3_N
AB13
AC13 PEX_TX4
C
PEX_TX4_N C
+3.3V_1.8V_AON
AF10
9 PCIE4_CRX_GTX_N[0..3] PEX_RX4
AE10
PEX_RX4_N
9 PCIE4_CRX_GTX_P[0..3]
AD14 OPTN16@
AC14 PEX_TX5 AA8 PEX_PLL_HVDD RV2008 1 2 0_0402_5% PEX_PLL_HVDD
9 PCIE4_CTX_C_GRX_N[0..3] PEX_TX5_N PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
AA9 +3V_1.8VGS N16:+3.3V_AON
AE12
N17:+1.8VGS

0.1U_6.3V_K_X5R_0201
9 PCIE4_CTX_C_GRX_P[0..3] PEX_RX5
AF12 1 OPTN17@
PEX_RX5_N

CV2027
RV2009 1 2 0_0402_5%

OPT@
AC15
AB15 PEX_TX6
PEX_TX6_N 2 Change by Bourne 20170412
AG12
AG13 PEX_RX6
PEX_RX6_N
AB16
AC16 PEX_TX7
PEX_TX7_N
Under GPU PEX_DVDD/Q Decouling
AF13
AE13 PEX_RX7 (below 150mils)
PEX_RX7_N
AD17 MLCC N16 N17 location
AC17 PEX_TX8
PEX_TX8_N 1.0uF 1 1
AE15
PEX_RX8 Under
AF15
PEX_RX8_N 4.7uF 0 1
AC18
AB18 PEX_TX9
PEX_TX9_N
4.7uF 1 2 Near
AG15
AG16 PEX_RX9 10uF 0 2 Midway
PEX_RX9_N

PEX LANES 15 - 4 ARE DEFEATURED

AB19
PEX_TX10
22uF 0 1
AC19
PEX_TX10_N
AF16
B
AE16 PEX_RX10 B
PEX_RX10_N PEX_HVDD/Q Decouling
AD20
AC20 PEX_TX11

AE18
PEX_TX11_N
MLCC N16 N17 location
PEX_RX11
AF18
PEX_RX11_N 1.0uF 1 4 Under
AC21
AB21 PEX_TX12
PEX_TX12_N
4.7uF 1 2 Near
AG18
AG19 PEX_RX12 10uF 1 2 Midway
PEX_RX12_N
AD23
PEX_TX13
22uF 1 1
AE23
PEX_TX13_N
AF19
AE19 PEX_RX13
PEX_RX13_N
AF24
AE24 PEX_TX14
PEX_TX14_N
AE21
AF21 PEX_RX14
PEX_RX14_N PEX_PLL_HVDD/Q Decouling
AG24
AG25 PEX_TX15

AG21
PEX_TX15_N
MLCC N16 N17 location
PEX_RX15
AG22
PEX_RX15_N 0.1uF 1 1 Near
AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV2010
PEX_TERMP

N17S-G1-A1_GB2C-64-595 @
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_PCIE Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

UV1B ? COMMON INS35854731

2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
FBA_D2 E16 FBA_D1
27,28 FBA_D[0..63] FBA_D3 FBA_D2
F17
FBA_D4 D20 FBA_D3
27,28 FBA_CMD[31..0] FBA_D5 FBA_D4
D21
FBA_D6 F20 FBA_D5
27,28 FBA_EDC[7..0] FBA_D7 FBA_D6
E21
FBA_D8 E15 FBA_D7
27,28 FBA_DBI[7..0] FBA_D9 FBA_D8
D15
D FBA_D10 F15 FBA_D9 D
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13
FBA_D15 D13 FBA_D14
FBA_D16 B15 FBA_D15
FBA_D17 C16 FBA_D16
FBA_D18 A13 FBA_D17
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21
FBA_D23 C19 FBA_D22
FBA_D24 B24 FBA_D23 +1.35VGS
FBA_D25 C23 FBA_D24
FBA_D26 A25 FBA_D25
FBA_D27 A24 FBA_D26
FBA_D28 A21 FBA_D27
FBA_D29 B21 FBA_D28

1
FBA_D30 C20 FBA_D29
FBA_D31 FBA_D30 RV2101 RV2102
C21
FBA_D32 R22 FBA_D31 10K_0402_1% 10K_0402_1%
FBA_D33 FBA_D32 FBA_CMD0 OPT@ OPT@
R24 C27
FBA_D34 T22 FBA_D33 FBA_CMD0 C26 FBA_CMD1

2
FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_CMD2
FBA_D36 N25 FBA_D35 FBA_CMD2 F24 FBA_CMD3 FBA_CMD14
FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4
FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_CMD5 FBA_CMD30
FBA_D39 N24 FBA_D38 FBA_CMD5 F25 FBA_CMD6
FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_CMD7
FBA_D41 V22 FBA_D40 FBA_CMD7 F23 FBA_CMD8
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9 FBA_CMD13
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11 FBA_CMD29
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
FBA_D47 AA23 FBA_D46 FBA_CMD13 G27 FBA_CMD14

1
C FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CMD15 C
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16 RV2103 RV2104
AB25 M24
FBA_D50 AD26 FBA_D49 FBA_CMD16 M23 FBA_CMD17 10K_0402_1% 10K_0402_1%
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18 OPT@ OPT@
AC25 K24
FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19

2
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_CMD23
FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_CMD24
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26
FBA_D60 V26 FBA_D59 FBA_CMD26 J24 FBA_CMD27
FBA_D61 V27 FBA_D60 FBA_CMD27 K27 FBA_CMD28
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30 +1.35VGS
FBA_D63 FBA_CMD30 J26 FBA_CMD31
FBA_CMD31 B19
FBA_DBI0 D19 FBA_CMD32 F22 RV2105 2 @ 1 60.4_0402_1%
FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV2106 2 @ 1 60.4_0402_1%
FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
FBA_DBI3 C22 FBA_DQM2
FBA_DBI4 P24 FBA_DQM3
FBA_DBI5 W24 FBA_DQM4
FBA_DBI6 AA25 FBA_DQM5
FBA_DBI7 U25 FBA_DQM6
FBA_DQM7

FBA_EDC0 E19
FBA_EDC1 C15 FBA_DQS_WP0
FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0
FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 27
D25 FBA_CLK0#
FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK0# 27
N22 FBA_CLK1
FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 28
M22 FBA_CLK1#
FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 28
FBA_EDC7 T26 FBA_DQS_WP6
FBA_DQS_WP7
B B
F19 D18 FBA_WCLK01
FBA_DQS_RN0 FBA_WCK01 FBA_WCLK01# FBA_WCLK01 27
C14 C18
FBA_DQS_RN1 FBA_WCK01_N FBA_WCLK23 FBA_WCLK01# 27
A16 D17
FBA_DQS_RN2 FBA_WCK23 FBA_WCLK23# FBA_WCLK23 27
A22 D16
FBA_DQS_RN3 FBA_WCK23_N FBA_WCLK45 FBA_WCLK23# 27
P25 T24
FBA_DQS_RN4 FBA_WCK45 FBA_WCLK45# FBA_WCLK45 28
W22 U24
FBA_DQS_RN5 FBA_WCK45_N FBA_WCLK67 FBA_WCLK45# 28 PEX_HVDD
AB27 V24
FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28
T27 V25 +FB_PLLAVDD Place close to BGA
FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28 200mA
Near GPU LV2101 PEX_HVDD
F16 Under GPU 2 1 N16:+1.05VGS(recommend)
FB_PLL_AVDD_1 +1.0VGS(Used)

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
SBK160808T-300Y-N
P22 +FB_PLLAVDD N17:+1.8VGS

CV2101 OPT@

CV2102 OPT@

CV2103 OPTN17@

CV2104 OPTN17@

CV2105 OPT@
22U_0603_6.3V6-M
FB_PLL_AVDD_2 OPT@
Place close to ball 1
H22 1 1 1 1
FB_REFPLL_AVDD 30ohms (ESR=0.01) 0603 Bead
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

2
CV2106 OPT@

CV2107 OPTN17@

CV2108 OPTN17@

2 2 2 2
1 1 1

2 2 2
D23
FB_VREF

N17S-G1-A1_GB2C-64-595 @

N17S Add 2x0.1u

FB_PLL/Q Decouling
MLCC N16 N17 location
A A
0.1uF 2 4 Under

22uF 1 1 Near

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
+VGA_CORE
Under GPU 12x4.7uF 5x1uF
+VGA_CORE CV2201 CV2202 CV2203 CV2204 CV2205 CV2206 CV2207 CV2208 CV2209 CV2210 CV2211 CV2212 CV2213 CV2214 CV2215 CV2216 CV2217 CV2218
UV1C ? COMMONINS37185662
UV1G ? COMMON INS35856873

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
11/14 NVVDD

33P_0402_50V8J
6/14 XVDD K10

OPTN17@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

OPTNS@

OPTN17@

OPTNS@

OPTNS@

OPTN17@
K12 VDD_001

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT_RF@
K14 VDD_002
G1 N4 VDD_003
XVDD_1 XVDD_36 K16
G2 N5 VDD_004 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
XVDD_2 XVDD_37 K18
G3 N7 VDD_005
XVDD_3 XVDD_38 L13
G4 P3 VDD_006
XVDD_4 XVDD_39 L15
D G5 P4 VDD_007 D
XVDD_5 XVDD_40 M10
G6 P6 VDD_008
XVDD_6 XVDD_41 M12
G7 R1 VDD_009
XVDD_7 XVDD_42 M16
H3 R2 VDD_010
XVDD_8 XVDD_43 M18
H4 R3 VDD_011
XVDD_9 XVDD_44 N11
H6 R4 VDD_012
XVDD_10 XVDD_45 N13
J1 R5 VDD_013 Near GPU 4x4.7uF 11x10uF 4x22uF
XVDD_11 XVDD_46 N15
J2 R6 VDD_014
XVDD_12 XVDD_47 N17
J3 R7 VDD_015 CV2219CV2220 CV2221 CV2222 CV2223 CV2224 CV2225 CV2226 CV2227 CV2228 CV2229 CV2230 CV2231 CV2232 CV2233 CV2234 CV2235 CV2236 CV2237 CV2238 CV2239 CV2240
XVDD_13 XVDD_48 P14
J4 T1 VDD_016
XVDD_14 XVDD_49 R11
J5 T2 VDD_017
R13

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

J6 XVDD_15 XVDD_50 T3

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
R15 VDD_018

OPTN17_NS@

OPTN17_NS@

OPTN17_NS@
J7 XVDD_16 XVDD_51 T4

OPTN17_NS@

OPTN17@

OPTN17@

RF_NS@
R17 VDD_019 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2

OPTNS@

OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTNS@

OPTN17@

OPTNS@

OPTNS@
K1 XVDD_17 XVDD_52 T5

OPT@

OPT@

OPT@
T10 VDD_020
K2 XVDD_18 XVDD_53 T6
T12 VDD_021
K3 XVDD_19 XVDD_54 T7
T16 VDD_022
K4 XVDD_20 XVDD_55 U3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
T18 VDD_023
K5 XVDD_21 XVDD_56 U4
U13 VDD_024
K6 XVDD_22 XVDD_57 U6
U15 VDD_025
K7 XVDD_23 XVDD_58 V1
V10 VDD_026
L3 XVDD_24 XVDD_59 V2 +VGA_CORE
V12 VDD_027 CV88 Use virtual Symbol for diff value
L4 XVDD_25 XVDD_60 V3
V14 VDD_028
M1 XVDD_26 XVDD_61 V4
V16 VDD_029
M2 XVDD_27 XVDD_62 V5 RV2201 1 @ 2 0_0402_5%
V18 VDD_030
M3 XVDD_28 XVDD_63 V6 RV2202 1 2 0_0402_5%
M4 XVDD_29 XVDD_64 V7 @ VDD_031 NVVDD/Q Decouling
M5 XVDD_30 XVDD_65 W1
M7 XVDD_31 XVDD_66 W2
N1 XVDD_32 XVDD_67 W3 VDD_SENSE
F2
F1
NVVDD_VCC_SENSE
NVVDD_VSS_SENSE NVVDD_VCC_SENSE 58 MLCC N16 N17 location
N2 XVDD_33 XVDD_68 W4 NVVDD_VSS_SENSE 58
GND_SENSE
XVDD_34 XVDD_69
N3
XVDD_35 4.7uF 10 12
trace width: 16mils
differential voltage sensing.
Under
differential signal routing. 1.0uF 4 5

N17S-G1-A1_GB2C-64-595
N17S-G1-A1_GB2C-64-595 47uF 1 0
C C

@
@

10uF 0 11
Near
22uF 1 4
4.7uF 5 4
330uF 1 2
+1.35VGS

UV1D ? COMMON INS35857178

12/14 FBVDDQ

B26 +1.35VGS
C25 FBVDDQ_01
E23 FBVDDQ_02 +VGA_CORE
FBVDDQ_03 1x10uF 3x22uF
E26
F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU UV1F ? COMMON INS35856561
F21 FBVDDQ_05 CV2247 CV2241 CV2242 CV2243 CV2244 CV2248 CV2245 CV2249 CV2250 CV2251 CV2252 CV2253 CV2254 CV2246
FBVDDQ_06 7/14 VDDS
G13
G14 FBVDDQ_07
0.1U_6.3V_K_X5R_0201

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U 6.3V M X5R 0402

G15 FBVDDQ_08 L11
10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

OPTN17_NS@
OPTN17@
G16 FBVDDQ_09 1 1 1 2 L17 VDDS_1
OPTN17@

OPTN17@

OPTN17@
1 2 1 1 1 1 1 1 1 1
OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPT@

OPT@
G18 FBVDDQ_10 M14 VDDS_2
OPT@
OPTNS@

OPT@

G19 FBVDDQ_11 P10 VDDS_3

G20 FBVDDQ_12 P12 VDDS_4
FBVDDQ_13 2 2 2 1 VDDS_5
G21 2 1 2 2 2 2 2 2 2 2 P16
L22 FBVDDQ_14 P18 VDDS_6
L24 FBVDDQ_19 T14 VDDS_7
L26 FBVDDQ_20 U11 VDDS_8
M21 FBVDDQ_21 U17 VDDS_9
N21 FBVDDQ_22 VDDS_10
B
R21 FBVDDQ_23 B
FBVDDQ_24 CV32 CV686 Use virtual Symbol for diff value
T21
V21 FBVDDQ_25
W21 FBVDDQ_26
H24 FBVDDQ_27 FBVDD/Q Decouling
H26 FBVDDQ_15
J21 FBVDDQ_16 F4 1 TV2201 @
K21 FBVDDQ_17 MLCC N16 N17 location VDDS_SENSE F3 FB_CLAMP RV2203 1 OPTN16@2 10K_0402_5%
FBVDDQ_18 GNDS_SENSE

0.1uF 2 0 N17S-G1-A1_GB2C-64-595

@
1.0uF 2 8
Under
4.7uF 2 0
10uF 0 2
10uF 1 1
Near
22uF 1 3
+1.35VGS

FB_CAL_PD_VDDQ
D22 RV2204 1 OPT@ 2 40.2_0402_1% CALIBRATION PIN GDDR5

FB_CAL_PU_GND
C24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
A A

FB_CAL_TERM_GND
B25 RV2206 1 OPT@ 2 60.4_0402_1% FB_CAL_x_PU_GND 40.2Ohm
Place near balls
FB_CAL_xTERM_GND 60.4Ohm

Security Classification LC Future Center Secret Data Title

N17S-G1-A1_GB2C-64-595
Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_+VGA_CORE,FBVDDQ
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

N16 3V3_MAIN(N17 VDD_18) Decouling Discharge

+3V_1.8VGS
+5VALW
Under GPU Near GPU MLCC N16 N17 location +1.35VGS
@
UV1E ? COMMON INS35858730 +VDD18 RV2301 1 2 0_0402_5%

1
14/14 VDD18
0.1uF 2 2 Under

CV2301
0.1U_6.3V_K_X5R_0201

CV2302
0.1U_6.3V_K_X5R_0201

CV2303
1U_6.3V_M_X5R_0201

CV2304
4.7U_0402_6.3V6M
RV2302
RV2303
G8 1 1 1 1
VDD18_1 47K_0402_5% 470_0603_5%
G9
VDD18_2
1V8_AON_1
G10 1.0uF 1 1 OPTNS@ OPTNS@
G12 Near

3 2
1V8_AON_2 2 2 2 2

OPT@

OPT@

OPT@

OPT@
D
4.7uF 1 1 FBVDDQ_PWR_EN# 5 QV2301B
G
D LBSS138DW1T1G_SOT363-6

6
S

4
D FBVDDQ_PWR_EN 2 OPTNS@ D
QV2301A
G
+3.3V_1.8V_AON S LBSS138DW1T1G_SOT363-6
N16 3V3_AON(N17 1V8_AON) Decouling

1
OPTNS@
Under GPU Near GPU
VDD_AON RV2304 1 @ 2 0_0402_5%
MLCC N16 N17 location

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201
CV2305
0.1U_6.3V_K_X5R_0201

CV2306 OPTN17@

CV2307 OPT@

CV2308 OPT@
4.7U_0402_6.3V6M
N17S-G1-A1_GB2C-64-595 1 1 1 1 0.1uF 1 2 Under +5VALW +3.3V_1.8V_AON
@

2
1.0uF 1 1
OPT@

1
2 2 2 2 RV2305
Near 47K_0402_5%
RV2306
470_0603_5%
4.7uF 1 1 OPTNS@ OPTNS@

3 2
D
PXS_PWREN# 5 QV2302B
G
2N7002KDWH_SOT363-6

6
D
PXS_PWREN 2 QV2302A S OPTNS@
PXE_VDD & 1V8_AON

4
G +3V_1.8VGS
2N7002KDWH_SOT363-6
S OPTNS@

1
PXS_PWREN RV2307 1 @ 2 0_0402_5%PXS_PWR_EN_R

1
8 PXS_PWREN PXS_PWR_EN_R 57 1
RV2308 CV2309
470_0603_5% 10U 6.3V M X5R 0402

1
OPTNS@ GC6@
RV2309 2
100K_0402_5%

2
@

1
D
2

2 OPTNS@
G
C QV2303 C

+3VS S L2N7002KWT1G_SOT323-3
DV2301 @ +3.3V_1.8V_AON

3
DGPU_PWROK 1 2
2

1 2
RB521CM-30T2R_VMN2M-2 RV2310 RV2311
10K_0402_5% 10K_0402_5%
@ OPT@ RV2316 建虚拟料号,N16=470 ohm,N17=5.11 ohm
1

DV2302 +5VALW +1.0VGS

PXS_PWREN 2 RV2313
RV2312 1 PXE_VDD_EN 2 1 PXE_VDD_EN_R RV109 change to 470ohm 0805 for N16 GPU
1.8VGS_PWR_EN PXE_VDD_EN_R 57
1 2 3
30K_0402_5%
OPT@
1

0_0402_5% LBAT54AWT1G_SOT323-3 2

1
@ OPT@ RV2314

1
10K_0402_5% D2301 OPT@ CV2310 RV2317
0.22U_0402_10V6K RV2315 RV2316 470_0805_5%
@ 1 47K_0402_5% 5.11_0805_1%
1 2 OPT@
2

OPT@ OPTN17@ @

2
1 2

2
RB521CM-30T2R_VMN2M-2

+1.8VG_AON TO +1.8VGS

1
D
+1.0VGS_PWR_EN# 2 QV2304
G AO3402_SOT-23-3
OPTN17@

S
+3VS
D

3
1
1

PXE_VDD_EN_R 2 QV2305
RV2318 G LBSS139WT1G_SC70-3
B B
82K_0402_1% OPT@ S
D

1
@
@ 2 QV2306
DV2303
2

PXS_PWREN G LBSS139WT1G_SC70-3
RV2321 1 @ 2 0_0402_5% 2
NVVDD_EN OPTN16@ S
1

3
1.8VGS_PWR_EN NVVDD_EN 58
RV2323 1 OPT@ 2 0_0402_5% 3
26,57 1.8VGS_PWR_EN
RV2324 1 @ 2 0_0402_5% LBAT54AWT1G_SOT323-3
1

+3V_1.8VGS
RV2325
RV2326 1 OPT@ 2 0_0402_5% 100K_0402_1%
@
2

+5VALW +VGA_CORE

1
RV2327
47K_0402_5% RV2328
OPTNS@ 10_0603_5%
OPTNS@

3 2
D
NVVDD_EN# QV2309B
5
DV2304 G LBSS138DW1T1G_SOT363-6
D

6
FB_GC6_EN_R RV2329 1 GC6@ 2 0_0402_5% GC6_EN 2 S OPTNS@
8,26 FB_GC6_EN_R

4
1 FBVDDQ_PWR_EN FBVDDQ_PWR_EN 57 NVVDD_EN 2 QV2309A
DGPU_PWROK OPT@
RV2330 1 2 10K_0402_5% 3 G
8,58 DGPU_PWROK LBSS138DW1T1G_SOT363-6
S

1
1

BAV70W-7-F_SOT323-3 OPTNS@
RV2333
GC6@
CV2313 OPT@
0.1U_6.3V_K_X5R_0201

200K_0402_5%
1 GC6@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

UV1H ? COMMON INS35859464

13/14 GND

D D
A2 K11
AB17 GND_001 GND_057 K13
AB20 GND_005 GND_058 K15
AB24 GND_006 GND_059 K17
AC2 GND_007 GND_060 L10
AC22 GND_008 GND_061 L12
AC26 GND_009 GND_062 L14
AC5 GND_010 GND_063 L16
AC8 GND_011 GND_064 L18
AD12 GND_012 GND_065 L5
AD13 GND_013 GND_069 M11
A26 GND_014 GND_070 M13
AD15 GND_002 GND_071 M15
AD16 GND_015 GND_072 M17
AD18 GND_016 GND_073 N10
AD19 GND_017 GND_074 N12
AD21 GND_018 GND_075 N14
AD22 GND_019 GND_076 N16
AE11 GND_020 GND_077 N18
AE14 GND_021 GND_078 P11
AE17 GND_022 GND_079 P13
AE20 GND_023 GND_080 P15
AB11 GND_024 GND_081 P17
AF1 GND_003 GND_082 P23
AF11 GND_025 GND_084 P26
AF14 GND_026 GND_085 R10
AF17 GND_027 GND_087 R12
AF20 GND_028 GND_088 R14
AF23 GND_029 GND_089 R16
AF5 GND_030 GND_090 R18
AF8 GND_031 GND_091 T11
AG2 GND_032 GND_092 T13
AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
B11 GND_035 GND_096 U12
B14 GND_036 GND_097 U14
C B17 GND_037 GND_098 U16 C
B20 GND_038 GND_099 U18
B23 GND_039 GND_100 U23
B27 GND_040 GND_102 U26
B5 GND_041 GND_103 V11
B8 GND_042 GND_105 V13
E11 GND_043 GND_106 V15
E14 GND_044 GND_107 V17
E17 GND_045 GND_108 Y2
E2 GND_046 GND_109 Y23
E20 GND_047 GND_110 Y26
E22 GND_048 GND_111 Y5
E25 GND_049 GND_112 AA7
E5 GND_050 GND_F AB7
E8 GND_051 GND_H
GND_052

H2 P2
H5 GND_053 GND_083 P5
L2 GND_056 GND_086 U2
GND_066 GND_101 U5
GND_104

H23 L23
H25 GND_054 GND_067 L25
GND_055 GND_068

N17S-G1-A1_GB2C-64-595
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

PEX_PLLVDD/Q Decouling
MLCC N16 N17 location UV1J ? COMMON INS35860124
4/14 IFPAB

1.0uF 1 NA Under DVI HDMI DP

SL/DL
1uF 1 NA AC4
Near TXC/TXC
IFPA_L3_N AC3
4.7uF 1 NA IFPA_L3
AA6
IFPAB_RSET Y3
TXD0/0
UV1I ? COMMON INS35860218 IFPA_L2_N Y4
D +1.0VGS
IFPA_L2 D
5/14 NC
OPTN16@
TXD1/1 AA2
RV2501 2 1 0_0402_5% Under GPU Near GPU +PEX_PLLVDD +PEX_PLLVDD AA14 W7 IFPA_L1_N AA3
AA15 NC_1 IFPAB_PLLVDD IFPA_L1

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

4.7U_0402_6.3V6M
AB6 NC_2

CV2501 OPTN16@

CV2502 OPTN16@

CV2503 OPTN16@
PEX_SVDD_3V3 AB8 NC_3 AA1
TXD2/2
1 1 1 AD10 NC_4 IFPA_L0_N AB1
AD7 NC_5 IFPA_L0
PEX_PLLVDD 1 @ 2 PEX_TSTCLK_OUT AE22 NC_6
N16:+1.0VGS(recommend) RV2502 200_0402_1% AE3 NC_7 AA5
2 2 2 NC_8 IFPA_AUX_SDA_N
N17:NC AE4 AA4
+3.3V_1.8V_AON AF2 NC_9 IFPA_AUX_SCL
PEX_TSTCLK_OUT# AF22 NC_10
AF3 NC_11 AB4
NC_12 IFPB_L3_N

1
+3.3V_1.8V_AON Differential signal AF4 TXC AB5
RV2503 AG3 NC_13 IFPB_L3
10K_0402_5% D10 NC_14
@ E10 NC_15 W6 AB2
TXD0/3
F10 NC_16 IFP_IOVDD_1 IFPB_L2_N AB3
NC_17 IFPB_L2

2
F5 Y6
MULTI_STRAP_REF0_GND F6 NC_18 IFP_IOVDD_2
OPTN16@ NC_19
RV2504 2 1 0_0402_5% PEX_SVDD_3V3 W5 TXD1/4 AD2
NC_20 IFPB_L1_N AD3
IFPB_L1
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1
OPTN16@

OPTN16@

1 1 RV2505
40.2K_0402_1% TXD2/5 AD1
OPTN16@ IFPB_L0_N AE1
PEX_SVDD_3V3 N17S-G1-A1_GB2C-64-595 IFPB_L0
CV2504

CV2505

N16:+3.3V_AON(recommend) 2 2

@
N17:NC AD5
IFPB_AUX_SDA_N AD4
Change by Bourne 20170412 IFPB_AUX_SCL
Change by Bourne 20170412 Near GPU
IFPAB (DEFEATURED 0N GM108)

C
PEX_SVDD/Q Decouling C
N17S-G1-A1_GB2C-64-595
UV1K ? COMMON INS35860067

@
MLCC N16 N17 location 10/14 MISC2

4.7uF 2 NA Near
D12 1
ROM_CS_N TV2501 @
B12 ROM_SI
ROM_SI ROM_SO ROM_SI 29
A12
ROM_SO ROM_SCLK ROM_SO 29
STRAP0 D1 C12
29 STRAP0 STRAP0 ROM_SCLK ROM_SCLK 29
STRAP1 D2
29 STRAP1 STRAP1
STRAP2 E4
29 STRAP2 STRAP2
STRAP3 E3
29 STRAP3 STRAP3
STRAP4 D3
29 STRAP4 STRAP4
STRAP5 C1
29 STRAP5 STRAP5

D11 RV2506 2 @ 1 10K_0402_5%

BUFRST_N

XS_PLLVDD/Q Decouling
MLCC N16 N17 location
PEX_HVDD
N16:+1.05VGS(recommend) 0.1uF 1 1 Under
+1.0VGS(Used)
N17:+1.8VGS 22uF 1 0 Near
PEX_HVDD N17S-G1-A1_GB2C-64-595

@
LV2501
1 2 OPT@ LV2502 1 @ 2 0_0402_5% Under GPU XS_PLLVDD
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

SBK160808T-300Y-N UV1L ? COMMON INS35860348

CV2509
22U_0603_6.3V6-M

B B
CV2508
4.7U_0402_6.3V6M

CV2507 OPT@

CV2506

1 1 9/14 XTAL_PLL
30ohms (ESR=0.05) Bead 1 1 SP_PLLVDD & VID_PLLVDD/Q Decouling XS_PLLVDD L6
SP_PLLVDD M6 XS_PLLVDD +3.3V_1.8V_AON
2 2 MLCC N16 N17 location GPCPLL_AVDD F11 SP_PLLVDD
OPT@

2 2 @ VID_PLLVDD N6 GPCPLL_AVDD
OPT@

VID_PLLVDD

2
0.1uF 2 2 Under
150mA RV2507
10K_0402_5%
10uF 1 0 @
Near

1
Change by Bourne 20170412 Under GPU(below 150mils)
47uF 1 0 10K_0402_5% 2 OPT@ 1 RV2508 XTALSSIN A10
XTAL_SSIN XTAL_OUTBUFF
C10 XTALOUT

LV2503 1 @ 2 0_0402_5% SP_PLLVDD

1
XTAL_IN C11 B10 XTAL_OUT
XTAL_IN XTAL_OUT RV2509
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

N17S-G1-A1_GB2C-64-595 10K_0402_5%
OPTN17@
CV2510 OPT@

CV2511 OPT@

1 1 OPT@

@
RV2510 1 2 0_0402_5% VID_PLLVDD

2
2 2 RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT

2
R2501
51_0402_1%
YV2501
OPT@

1
OPTN17@ XTAL_IN 1 4
LV2504 1 2 0_0402_5% GPCPLL_AVDD OSC1 GND2
2 3 XTAL_OUT_R
GND1 OSC2
0.1U_6.3V_K_X5R_0201

1
12P_0402_50V8-J

12P_0402_50V8-J
OPT@

GPCPLL_AVDD/Q Decouling
CV2512 OPTN17@

OPT@
1 1
27MHZ_10PF_7V27000050
OPT@
2
MLCC N16 N17 location 2 2
CV2513

CV2514
A A

0.1uF NA 1 Under

4.7uF NA 1
Near
22uF NA 1
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_STRAP/DP/HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

UV1M ? COMMON INS35861009

8/14 MISC1
+3.3V_1.8V_AON +3.3V_1.8V_AON
GPU Address 0x9E

3
4
D9 VGA_SMB_CLK
I2CS_SCL D8 VGA_SMB_DATA Internal Thermal Sensor RPV4

2
I2CS_SDA 2.2K_0404_4P2R_5%
OVERT# A6 QV2601A
OVERT OPT@
AE2 A9 I2CC_SCL PJT7838_SOT363-6

G1
TS_VREF I2CC_SCL B9 I2CC_SDA OPT@

2
1
I2CC_SDA VGA_SMB_CLK 1 6
S1 D1 EC_SMB_CK0 39,44

0.1U_6.3V_K_X5R_0201
CV2601
D 1 E12 D
THERMDN C9 I2CB_SCL
F12 I2CB_SCL C8 I2CB_SDA

5
THERMDP I2CB_SDA
2 QV2601B

G2
@ PJT7838_SOT363-6
VGA_SMB_DATA 4 3 OPT@
S2 D2 EC_SMB_DA0 39,44

C6 NVVDD_PWM_VID
GPIO0 FB_GC6_EN NVVDD_PWM_VID 58 PU AT EC SIDE, +3VS AND 4.7K
B2
GPIO1 D6 GPU_EVENT#_R
GPIO2 C7 NVVDDS_PWM 1
GPIO3 1.8VGS_PWR_EN_R TV2601
PLT_RST_VGA# @ F9
RV2605 1 2 56_0402_5% GPIO4 A3
1 GPIO5 A4 PSI_VGA
CV2602 GPIO6 PSI_VGA 58
B6
220P_0201_25V7-K GPIO7 MEM_VDD_CTL
E9
@ GPIO8 VGA_ALERT#
2 F8
2

GPIO9 C5 GPIO10_FBVREF_ALTV +3.3V_1.8V_AON +3VALW +3VS

GPIO10 GPIO10_FBVREF_ALTV 27
E7
GPIO11 D7 VGA_AC_DET_R 2 1
VGA_AC_DET 44

2
OVERT# 3 1 GPIO12 DV2601 OPT@ RV2606
WRST# 44 B4
GPIO13 RB751V-40_SOD323-2 10K_0402_5%
B3
1 GPIO14 GC6N17@

2
C3 RV2609
CV2603 GPIO15 SYS_PEX_RST_MON#_GPU
QV2602 D5 RV2607 1 2 0_0402_5% SYS_PEX_RST_MON# RV2608 10K_0402_5%
0.01U_0201_10V6K GPIO16 FB_GC6_EN_R
D4 OPTN16@ 10K_0402_5% GC6N17@

1
@ LSI1012XT1G_SC-89-3 GPIO17 FB_GC6_EN_R 8,23
2 C2 @
@ GPIO18 F7
GPIO19

1
E6

3
GPIO20 GPU_PEX_RST_HOLD#_GPU GPU_PEX_RST_HOLD# QV2603B
C4 RV2610 1 2 0_0402_5%
GPIO21 A7 VGA_CRT_DATA OPTN16@

D2
GPIO22 VGA_CRT_CLK 5 PJT7838_SOT363-6
B7 G2
GPIO23
GC6N17@

S2
6
N17S-G1-A1_GB2C-64-595
QV2603A

4
@

D1
FB_GC6_EN 2 PJT7838_SOT363-6
C G1 C
@
MEM_VDD_CTL 2 0_0402_5% SYS_PEX_RST_MON#

S1
RV2611 1

2
RV2612 GC6N17@

1
10K_0402_5%
GC6@

1
UV1N ? COMMON INS35861249
3/14 JTAG +3.3V_1.8V_AON GC6N16@
RV2613 1 2 0_0402_5%
2.2K_0404_4P2R_5%
1 AE5 VGA_CRT_DATA 2 3
TV2602 JTAG_TCK VGA_CRT_CLK
1 AE6 1 4
TV2603 JTAG_TDI
1 AF6 @
TV2604 JTAG_TDO RPV1
1 AD6
TV2605 JTAG_TMS 2.2K_0404_4P2R_5%
10K_0402_5% 2 OPT@ 1 RV2614 AG4
10K_0402_5% 2 OPT@ 1 RV2615 TESTMODE AD9 JTAG_TRST_N I2CB_SCL 2 3
NVJTAG_SEL I2CB_SDA 1 4 +3.3V_1.8V_AON +3.3V_1.8V_AON
@ RPV2

0.1U_6.3V_K_X5R_0201
1
2.2K_0404_4P2R_5%

CV2604
2
I2CC_SCL 2 3
I2CC_SDA RV2616
1 4
10K_0402_5% 2
@
RPV3 GC6@
@

2
MEM_VDD_CTL RV2617 1 @ 2 10K_0402_5%
+3.3V_1.8V_AON

N17S-G1-A1_GB2C-64-595 GPU_EVENT#_R 3 1 GPU_EVENT#

GPU_EVENT# 8
@

1.8VGS_PWR_EN_R RV2618 2 OPT@ 1 1K_0402_1%

GC6@
QV2604
OVERT# RV2619 1 OPT@ 2 10K_0402_5% LSI1012XT1G_SC-89-3

VGA_ALERT# RV2621 1 @ 2 0_0402_5%

RV26201 OPT@ 2 10K_0402_5%
B B
VGA_AC_DET_R RV26221 OPT@ 2 100K_0402_5%
PSI_VGA RV26231 @ 2 10K_0402_5%
GPU_PEX_RST_HOLD# RV26241 OPT@ 2 10K_0402_5% +3VS
+3VS

2
RV2625
10K_0402_5%
OPT@

2
RV2626
10K_0402_5%
OPT@ 1.8VGS_PWR_EN

1
+3VS 1.8VGS_PWR_EN 23,57

1
2

3
RV2627 QV2605B

D2
0_0402_5% 5 PJT7838_SOT363-6
+3.3V_1.8V_AON G2
@
0.1U_6.3V_K_X5R_0201

OPT@

S2
+3.3V_1.8V_AON
+1.8VGARST 1

CV2605 OPT@

4
2

QV2605A

D1
RV2629 1.8VGS_PWR_EN_R 2 PJT7838_SOT363-6
2 G1
2

RV2628 10K_0402_5%
10K_0402_5% OPT@ OPT@

S1
OPTN16@ DV2602
1
5

UV2603 GPU_PEX_RST_HOLD# 2

1
PLT_RST# 1 1
11,37,40,44 PLT_RST#
P

B PLT_RST_VGA# 20
1

4 SYS_PEX_RST_MON# 3
2 Y
8 PXS_RST# A
G

LBAT54AWT1G_SOT323-3
1

MC74VHC1G09DFT2G_SC70-5 OPTN16@
3

OPT@ OPTNS@
RV2630
1

1.8VGS_PWR_EN_R RV2632 1 2 0_0402_5% 1.8VGS_PWR_EN

100K_0402_5% RV2631 1 2 0_0402_5%
RV2633
OPT@
A 100K_0402_5% OPTN17@ A
2

OPT@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GPIO/JTAG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
Document Number
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

Lower 32 bits
MF=0 No Mirror
21,28 FBA_D[0..63]
+1.35VGS
21,28 FBA_CMD[31..0]
UM2701
21,28 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0 Close to VRAM
21,28 FBA_DBI[7..0]
A4 FBA_D0 CV2703 CV2704 CV2705 CV2701 CV2702 CV2706 CV2707
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
D FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 D
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 1 1 1 1 1 1 1
BYTE0

OPT_NS@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4

OPT@
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
DQ29 DQ5 F4 FBA_D6
DQ30 DQ6 2 2 2 2 2 2 2
FBA_DBI0 D2 F2 FBA_D7
FBA_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D8
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
OPT@ FBA_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
FBA_CLK0 RV2702 1 2 40.2_0402_1% DBI3# DBI0# DQ18 DQ10 B13 FBA_D11
21 FBA_CLK0
FBA_CLK0 DQ19 DQ11 FBA_D12
BYTE1
FBA_CLK0# J12 E11
RV2701 1 OPT@ 2 40.2_0402_1% FBA_CLK0# CK DQ20 DQ12 FBA_D13
21 FBA_CLK0# J11 E13
FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14 CV2709 CV2710 CV2711 CV2712 CV2713 CV2714 CV2715
1 CKE# DQ22 DQ14 F13 FBA_D15
CV2708

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DQ23 DQ15 U11 FBA_D16

1U_6.3V_M_X5R_0201
0.01U_0201_10V6K FBA_CMD2 DQ8 DQ16 FBA_D17 1 1 1 1 1 1 1
H11 U13
OPT@

OPT_NS@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
FBA_CMD4 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D18

OPT_NS@
2 BA1/A5 BA3/A3 DQ10 DQ18
FBA_CMD3 K11 T13 FBA_D19
FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
BYTE2
H10 N11 2 2 2 2 2 2 2
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
DQ13 DQ21 M11 FBA_D22
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23
FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24
FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27
A12/RFU/NC DQ3 DQ27 N4 FBA_D28
BYTE3 Around VRAM
A5 DQ4 DQ28 N2 FBA_D29
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31 CV2716 CV2717 CV2718 CV2719 CV2720 CV2721 CV2722
DQ7 DQ31
RV27031 OPT@ 2 1K_1%_0201 J1 +1.35VGS

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
RV27041 OPT@ 2 1K_1%_0201 FBA_SEN0 J10 MF 1 1
SEN 1 1 1 1 1
RV2705 1 2 121_0402_1% OPT@ J13 B1

OPT@

OPT@

OPT@

OPT@

OPT@
ZQ VDDQ1 D1

OPT_NS@

OPT_NS@
VDDQ2 F1
VDDQ3 2 2
FBA_CMD8 J4 M1 2 2 2 2 2
FBA_CMD12 G3 ABI# VDDQ4 P1
C FBA_CMD0 G12 RAS# CAS# VDDQ5 T1 C
FBA_CMD15 L3 CS# WE# VDDQ6 G2
FBA_CMD5 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3
VDDQ10 F3
FBA_WCLK01# D5 VDDQ11 H3
21 FBA_WCLK01# FBA_WCLK01 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3
FBA_WCLK23# P5 VDDQ14 P3
21 FBA_WCLK23# FBA_WCLK23 WCK23# WCK01# VDDQ15
P4 T3
21 FBA_WCLK23 WCK23 WCK01 VDDQ16 E5
VDDQ17 N5
A10 VDDQ18 E10
FBA_VREFC VREFD1 VDDQ19
U10 N10
+1.35VGS FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
CV2723 1 VDDQ22 F12
820P_0402_25V7 VDDQ23 H12
VDDQ24
1

FBA_CMD13 J2 K12
RV2706 OPT@ RESET# VDDQ25 +1.35VGS
2 M12
549_0402_1% VDDQ26 P12
OPT@ VDDQ27 T12
VDDQ28 CV2724 CV2725 CV2726 CV2727 CV2728
G13
VDDQ29
1 2

FBA_VREFC H1 L13
K1 VSS1 VDDQ30 B14

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
VSS2 VDDQ31

4.3U_0402_4V6-M
B5 D14
RV2707

OPT_3T@
G5 VSS3 VDDQ32 F14 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@

3
1.33K_0402_1% VSS4 VDDQ33
L5 M14
OPT@ VSS5 VDDQ34
T5 P14
VSS6 VDDQ35
2

B10 T14 2 2 2 2

4
D10 VSS7 VDDQ36
G10 VSS8
L10 VSS9 A1
P10 VSS10 VSSQ1 C1
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
B K14 VSS13 VSSQ4 R1 B
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3
VDD2 VSSQ9 +1.35VGS
G4 C3
FBA_VREFC L4 VDD3 VSSQ10 E3
RV2708 C5 VDD4 VSSQ11 N3 CV2732 CV2733 CV2729 CV2730
VDD5 VSSQ12 CV2731
R5 R3
931_0402_1%

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
VDD6 VSSQ13

4.3U_0402_4V6-M
C10 U3
2 1

OPT_3T@
R10 VDD7 VSSQ14 C4 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@

3
D11 VDD8 VSSQ15 R4
OPT@ G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 2 2 2 2

4
P11 VDD11 VSSQ18 F10
D
1

QV2701 VDD12 VSSQ19

G14 M10
2 VDD13 VSSQ20
26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 C11
G VDD14 VSSQ21 R11
S OPT@ VSSQ22
1

A12
3

RV2709 VSSQ23 C12

100K_0402_5% VSSQ24 E12
OPT@ VSSQ25 N12
VSSQ26 R12
VSSQ27
2

170-BALL U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@ H5GQ1H24AFR-T2L_BGA170

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[31:0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

upper 32 bits

21,27 FBA_D[0..63] MF=0 No Mirror

21,27 FBA_CMD[31..0]
UM2801
21,27 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0
D 21,27 FBA_DBI[7..0] D
A4 FBA_D32
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
BYTE4
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D38
FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
FBA_CLK1 DQ19 DQ11 FBA_D44
BYTE5 +1.35VGS
J12 E11
FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45 Close to VRAM
FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_D46
FBA_CLK1 OPT@ CKE# DQ22 DQ14 FBA_D47
RV2801 1 2 40.2_0402_1% F13 CV2802 CV2803 CV2804 CV2805 CV2806 CV2807 CV2808
21 FBA_CLK1 DQ23 DQ15 FBA_D48
U11
FBA_CLK1# RV2802 1 OPT@ 2 40.2_0402_1% FBA_CMD18 H11 DQ8 DQ16 U13 FBA_D49
21 FBA_CLK1#

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
FBA_CMD20 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D50

10U 6.3V M X5R 0402

1 FBA_CMD19 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D51 1 1 1 1 1 1 1

OPT_NS@

OPT_NS@
OPT@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@
CV2801 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
BYTE6
N13
OPT@ DQ13 DQ21 M11 FBA_D54
2 DQ14 DQ22 2 2 2 2 2 2 2
FBA_CMD22 K4 M13 FBA_D55
FBA_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D56
FBA_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D59
A12/RFU/NC DQ3 DQ27 N4 FBA_D60
DQ4 DQ28 FBA_D61
BYTE7
A5 N2 CV2814 CV2809 CV2810 CV2811 CV2812 CV2813 CV2815
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
VPP/NC2 DQ6 DQ30 M2 FBA_D63

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DQ7 DQ31
1 1 1 1 1 1 1

OPT_NS@
RV28031 OPT@ 2 1K_1%_0201 J1 +1.35VGS

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
OPT@
RV28041 OPT@ 2 1K_1%_0201 FBA_SEN1 J10 MF
RV2805 1 2 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1 D1 2 2 2 2 2 2 2
C VDDQ2 F1 C
FBA_CMD24 J4 VDDQ3 M1
FBA_CMD28 G3 ABI# VDDQ4 P1
FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
FBA_CMD31 L3 CS# WE# VDDQ6 G2
FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3 Around VRAM
VDDQ10 F3
FBA_WCLK45# D5 VDDQ11 H3 CV2816 CV2817 CV2818 CV2819 CV2820 CV2821 CV2822
21 FBA_WCLK45# FBA_WCLK45 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK45 WCK01 WCK23 VDDQ13 M3

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
FBA_WCLK67# P5 VDDQ14 P3 1 1 1 1 1 1 1
21 FBA_WCLK67#

OPT@

OPT@

OPT@

OPT@
FBA_WCLK67 P4 WCK23# WCK01# VDDQ15 T3
21 FBA_WCLK67

OPT_NS@

OPT_NS@

OPT_NS@
WCK23 WCK01 VDDQ16 E5
VDDQ17 N5
FBA_VREFC VDDQ18 2 2 2 2 2 2 2
A10 E10
U10 VREFD1 VDDQ19 N10
FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
1 VDDQ22
CV2823 F12
820P_0402_25V7 VDDQ23 H12
FBA_CMD29 J2 VDDQ24 K12
OPT@ 2 RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14
L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 +1.35VGS
T5 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36
VSS8 CV2828
G10 CV2824 CV2825 CV2826 CV2827
L10 VSS9 A1
P10 VSS10 VSSQ1 C1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
B B
T10 VSS11 VSSQ2 E1

4.3U_0402_4V6-M
H14 VSS12 VSSQ3 N1

OPT_3T@
K14 VSS13 VSSQ4 R1 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_NS@

OPT_N3T@

3
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2 2 2 2 2

4
L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3
R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10 +1.35VGS
G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11
VSSQ22 CV2829 CV2830 CV2831 CV2832 CV2833
A12
VSSQ23 C12
VSSQ24 E12

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
VSSQ25

4.3U_0402_4V6-M
N12

OPT_NS@
VSSQ26 R12 1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

3
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13 2 2 2 2

4
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@
H5GQ1H24AFR-T2L_BGA170
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[64:32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON
X76
GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

2
RV2901 RV2902 RV2903 Samsung 8Gb K4G80325FB-HC28 0(0x0000) L L L
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L L H

1
D D

25 STRAP0 STRAP0
25 STRAP1 STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) L H L
25 STRAP2 STRAP2

2
RV2904 RV2905 RV2906
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

1
+3.3V_1.8V_AON
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

L L L 0 0 0 0
2

2
RV2907 RV2908 RV2909
100K_0402_5% 100K_0402_5% 100K_0402_5% 1: SMB_ALT_ADDR ENABLE
@ @ @
C 0: SMB_ALT_ADDR DISABLE C
1

1: DEVID_SEL REBRAND
25 STRAP3 STRAP3
25 STRAP4 STRAP4 0: DEVID_SEL ORIGNAL
25 STRAP5 STRAP5

1: PCIE_CFG LOW POWER

2

0: PCIE_CFG HIGH POWER

RV2910 RV2911 RV2912
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @ 1: VGA_DEVICE ENABLE
1

0: VGA_DEVICE DISABLE

Strap5 is NC pin on N16

DEVID_SEL
0 (Default)
B B
1

+3V_1.8VGS +3.3V_1.8V_AON PCIE_CFG

ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE 0 (Default)
2
2

RV2914
RV2913
0_0402_5%
0_0402_5%
OPTN17@ N17S-G1 H H M 0000 SOR0/1/2/3 DISABLE 1
OPTN16@
1
1

N16S-GTR SMBUS_ALT_ADDR
2

RV2915 RV2916 RV2917 0 0x9E (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1 0x9C (Multi-GPU usage)
1

25 ROM_SI
ROM_SI
ROM_SO
VGA_DEVICE
25 ROM_SO ROM_SCLK
25 ROM_SCLK 0 3D Device (Class Code 302h)
2

RV2918 RV2919 RV2920 1 VGA Device (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

+5VS
+3VS J1
+3VL 1
2 1
BEEP 3 2
4 3
RA3001 1 2 1K_0402_5% CA3001 1 2 0.1U_6.3V_K_X5R_0201 5 4
NOVO# R3001 1 2 200_0402_1% NOVO_BTN# 6 5
44 NOVO# EC_MUTE# 6
@ @ 7
44 EC_BEEP DA3001 44 EC_MUTE# 7
8
3 USB20_N6 9 8
D 9 USB20_N6 9 D

1
RA3008 USB20_P6 10

0_0201_5%
9 USB20_P6 10
1 RA3002 1 2 1K_0402_5% CA3002 1 2 0.1U_6.3V_K_X5R_0201 BEEP 11
12 11
CODEC_DMIC_CLK 12
@ 2 13
DMIC 3.3V Level CODEC_DMIC_DAT
14 13
14

2
BAT54CW_SOT323-3 15
DMIC_DATA @ DMIC_DAT_CON 6 HDA_BITCLK_AUDIO 15
@ RA3003 RA78 1 2 0_0201_5% 16
8 PCH_BEEP 6 HDA_SDOUT_AUDIO 16
10K_0402_5% 17
DMIC_CLK @ DMIC_CLK_CON 6 HDA_SDIN0 17
RA79 1 2 0_0201_5% 18
6 HDA_SYNC_AUDIO 18
RA3004 1 2 0_0201_5% @ 19
DVDD_IO 19

1
20
+1.8VS 20
RA81 2 @ 1 0_0201_5% 21
6 PCH_DMIC_DAT0 GND1
22
@ DMIC_DATA GND2
RA80 1 2 0_0201_5%
CODEC_DMIC_DAT
HIGHS_FC5AF201-1151H
ME@
@ DMIC_CLK
RA82 1 2 0_0201_5%
CODEC_DMIC_CLK
RA17 2 @ 1 0_0201_5%
6 PCH_DMIC_CLK0
CPU HDA BUS power 1.8VALW
+1.8VS +3VS
DMIC 1.8V Level +5VS

DVDD_IO +3VS J2

2.2K_0404_4P2R_5%

2.2K_0404_4P2R_5%
+1.8VALW +3VL

100P 25V J NPO 0201

100P 25V J NPO 0201

1mA 1
1

4
3

4
3
1 1 2
BEEP 3 2

RPA2

CA86

RPA3
RA3006 1 2 0_5%_0603 @ DVDD_IO 4 3

CA85
@ @ @ 5 4
+3VALW 2 2 NOVO_BTN# 6 5
6

1
2

1
2
2
+1.8VS EC_MUTE# 7
@ RA3007 8 7
RA3005 1 2 0.01_0603_1% 0_0402_5% UA5 USB20_N6 9 8
@
9

1
@ 1 8 USB20_P6 10
VCCA VCCB RA77 11 10
11

1
C DMIC_DATA 2 7 DMIC_DAT_CON DMIC_DAT_CON 0_0201_5% CODEC_DMIC_CLK 12 C
A0 B0 33 @ CODEC_DMIC_DAT 13 12
DMIC_CLK 3 6 DMIC_CLK_CON DMIC_CLK_CON 14 13
A1 B1 14

2
33 HDA_BITCLK_AUDIO 15
4 5 DMIC_OUTPUT_EN HDA_SDOUT_AUDIO 16 15
HDA_BITCLK_AUDIO GND OE HDA_SDIN0 17 16
HDA_SYNC_AUDIO 18 17
18

1
FXMA2102UMX_U-MLP8_1P2X1P4 19
DVDD_IO 19
1 @ RA76 20
+1.8VS 20
CA3003 100K_0201_5% ON/OFF 21 25
44,45 ON/OFF PWR_LED1# 21 GND1
33P_0402_50V8J @ 22 26
44 PWR_LED1# PWR_LED2# 22 GND2
EMC_NS@ 23
2 44 PWR_LED2# 23

2
24
+3VALW 24
add DMIC to PCH schematic for MS support HIGHSTAR_FC5AF241-2931H
ME@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 CODEC_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Blank
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

TPM
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
LCD POWER CIRCUIT CMOS Camera
+3VS +3VS_EDP
FI3301 W=40mils
CG3301 +LCDVDD_CON
1
W=60mils 1 2
UG3301

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
5 1

10U 6.3V M X5R 0402

0.047U_0402_16V7K
1 1A_32V_ERBRD1R00X

CI3301
D 2 IN OUT D

CI3302

CI3303
1 2
2

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

33P_0402_50V8J
GND
1 1 1 2
PCH_ENVDD 4 3

CG3302

CG3303

CG3304
4 PCH_ENVDD EN OCB 2 1
SY6288C20AAC_SOT23-5 @ @
2 2 2
@ @ CPU_EDP_TX0+ CG3305 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0+
4 CPU_EDP_TX0+
CPU_EDP_TX0- CG3306 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX0-
4 CPU_EDP_TX0-
EMI request
For RF CPU_EDP_TX1+ EDP_TX1+
CG3307 1 2 0.1U_6.3V_K_X5R_0201
V9B+ +LEDVDD 4 CPU_EDP_TX1+
FG3301 CPU_EDP_TX1- CG3308 1 2 0.1U_6.3V_K_X5R_0201 EDP_TX1-
4 CPU_EDP_TX1-
1 2

2200P_25V_K_X7R_0402
3A_32V_ERBRD3R00X
0.47U_0402_25V6K

CPU_EDP_AUX# CG3311 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUX#

CG3310
1 CG3309 1 4 CPU_EDP_AUX#
CPU_EDP_AUX CG3312 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUX JEDP1
4 CPU_EDP_AUX 1
2 2 +LEDVDD 1
2
3 2
4 3
5 4
EDP_TX0+ 6 5
EDP_TX0- 7 6
8 7
EMI Request
Camera @
EDP_TX1+
EDP_TX1-
9
10
8
9
RI3301 1 2 0_0402_5%
11 10
EDP_AUX 12 11
LI3301 EDP_AUX# 13 12
+3VS USB20_N5 1 2 USB20_N5_R 14 13
9 USB20_N5 1 2 14
DISPOFF# 15
C INVT_PWM 16 15 C
16
2

USB20_P5 4 3 USB20_P5_R CPU_EDP_HPD 17

9 USB20_P5 4 3 4 CPU_EDP_HPD 17
RG3302 18
PCH_ENBKL +LCDVDD_CON 18
RG3303 1 @ 2 0_0402_5% 4.7K_0402_5% EXC24CH900U_4P 19
4,44 PCH_ENBKL 19
@ @ 20
21 20
@ 21
1

RI3302 1 2 0_0402_5% DMIC_CLK_CON 22

@ 30 DMIC_CLK_CON DMIC_DAT_CON 22
BKOFF# RG3304 1 2 0_0402_5% DISPOFF# 23
44 BKOFF# 30 DMIC_DAT_CON 23
24
+3VS_EDP 24
25
26 25
27 26
+3VS USB20_P5_R 28 27
USB20_N5_R 29 28
30 29
EMI request 30
2

31
RG3305 32 G1
1K_0402_5% DMIC_DAT_CON DMIC_CLK_CON DISPOFF# INVT_PWM G2
@ DRAPH_FC5AF301-3181H
1 1 1 1 ME@
@
1

RG33061 2 0_0402_5% INVT_PWM

4 PCH_EDP_PWM
CG3410 CG3313 CG3314 CG3315
1

100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K

2 @ 2 @ 2 @ 2 @
RG3307
100K_0402_5%
2

B B
+3VS_TS

Touch Screen 1
JTS1

@ TS_EN 1
RG33111 2 0_0402_5% 2
8 PCH_TS_EN 2
3
+3VS_TS USB20_N3_CONN 4 3
USB20_P3_CONN 5 4
+3VS 6 5
6 7
GND1 8
@ USB20_P3_CONN GND2
RG33091 2 0_0402_5%
+3VS_TS RG3301
HIGHS_WS83061-S0171-HF
USB20_N3_CONN 1 2 ME@
AZ5725-01F.R7GR_DFN1006P2X2

1/10W_0_5%_0603
AZ5423-01F.R7GR_DFN1006P2E2

AZ5423-01F.R7GR_DFN1006P2E2
1

USB20_P3 4
LG3301
3 USB20_P3_CONN
+3VALW_PCH TS@ TS DISCHARGER
EMC_NS@

9 USB20_P3
1

4 3
DG3301

EMC_NS@

DG3302

EMC_NS@

DG3303

QG3303
@
USB20_N3 1 2 USB20_N3_CONN 3 1 +3VS_TS

D
9 USB20_N3 1 2
1
2

EXC24CH900U_4P RG3325 LP2301ALT1G_SOT-23-3

EMC_NS@ @ 100K_0201_5%

G
2

1
RG3326
@
2

RG33121 2 0_0402_5% RG3322 1 2 0_0402_5% RG3327 1 2 0_0402_5% VCC_TS_ON @ 100_0402_5%

1
@ @ CG3321

1 2
For EMI For ESD 0.1U_6.3V_K_X5R_0201
2 QG3305
@
1
1

QG3304 @ VCC_TS_ON 2
CG3320
0.1U_6.3V_K_X5R_0201 SSM3K15AMFV_2-1L1B
2

3
2 @
[8] VCC_TS_ON
A @ A
SSM3K15AMFV_2-1L1B
3
1

@ RG3323
100K_0402_5%
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

2
G
CPU_HDMI_TXP2 CG3401 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX2_DP_C
4 CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C
CG3402 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN2
CPU_HDMI_TXP1 CG3403 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX1_DP_C PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U

S
4 CPU_HDMI_TXP1 CPU_HDMI_TXN1 HDMI_TX1_DN_C 4 PCH_HDMI_DDC_DATA
1 2 0.1U_6.3V_K_X5R_0201

D
CG3404
4 CPU_HDMI_TXN1 QG3401A
2N7002KDWH_SOT363-6
CPU_HDMI_TXP0 CG3405 1 2 0.1U_6.3V_K_X5R_0201 HDMI_TX0_DP_C
4 CPU_HDMI_TXP0 CPU_HDMI_TXN0 HDMI_TX0_DN_C
CG3406 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_TXN0

5
G
D CPU_HDMI_CLKP HDMI_CLK_DP_C D
CG3407 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_CLKP CPU_HDMI_CLKN HDMI_CLK_DN_C
CG3408 1 2 0.1U_6.3V_K_X5R_0201
4 CPU_HDMI_CLKN
PCH_HDMI_DDC_CLK 4 3 DDPB_CLK_U

S
4 PCH_HDMI_DDC_CLK

D
QG3401B
2N7002KDWH_SOT363-6

+3VS
Need to change about 470Ohm 5%-575412 Page115 Rev0.8 RG3425 2 @ 1 0_0402_5%
HDMI_TX0_DP_C RG3401 1 2 470_0402_5%
+1.8VS
HDMI_TX0_DN_C RG3402 1 2 470_0402_5%
HDMI_TX1_DP_C RG3403 1 2 470_0402_5% RG34051 2 0_0402_5% @
HDMI_TX1_DN_C RG3404 1 2 470_0402_5%

2
HDMI_TX2_DP_C RG3406 1 2 470_0402_5% RG3408
1M_0402_5%

2
HDMI_TX2_DN_C RG3407 1 2 470_0402_5%
QG3403

1
HDMI_CLK_DP_C RG3409 1 2 470_0402_5%
CPU_HDMI_HPD 3 1 HDMI_DET
HDMI_CLK_DN_C 4 CPU_HDMI_HPD
RG3410 1 2 470_0402_5%

2
LSI1012XT1G_SC-89-3
1

D RG3411
+3VS
2 Maybe 2N7002 is ok? 20K_0402_5%
G QG3404
L2N7002KWT1G_SOT323-3

1
S
3

1 2
C RG3412 C
100K_0402_5%
@

RG3413 1 2 0_0402_5% @ HDMI_TX0_DP_CON

F1 use 1.1A
1

LG3401
HDMI_TX0_DP_C 4 3 RG3414
4 3 +5VS_HDMI_F +5VS_HDMI
270_0402_1% DG3401 +5VS
@ HDMI_CLK_DP_CON 1 1 10 9 HDMI_CLK_DP_CON
HDMI_TX0_DN_C 1 2 FG3401
1 2
2

HDMI_CLK_DN_CON 2 2 9 8 HDMI_CLK_DN_CON 1 3 1 2

S
EXC24CH900U_4P
EMC_HDMI@ HDMI_TX0_DP_CON 4 4 7 7 HDMI_TX0_DP_CON 1.1A_8V_1206L110THYR
RG3415

G
2
1 2 0_0402_5% @ HDMI_TX0_DN_CON HDMI_TX0_DN_CON 5 5 6 6 HDMI_TX0_DN_CON QG3402 1
LP2301ALT1G_SOT23-3 CG3409
3 3 0.1U_6.3V_K_X5R_0201
46 SUSP
8 2

AZ1045-04F_DFN2510P10E-10-9
RG3416 1 2 0_0402_5% @ HDMI_TX1_DP_CON EMC_NS@

LG3402
2

HDMI_TX1_DP_C 4 3 DG3402
4 3 RG3417 HDMI_TX1_DN_CON 1 1 10 9 HDMI_TX1_DN_CON
270_0402_1%
HDMI_TX1_DN_C 1 2 @
B 1 2 HDMI_TX1_DP_CON 2 2 9 8 HDMI_TX1_DP_CON B
+5VS_HDMI
1

EXC24CH900U_4P HDMI_TX2_DN_CON HDMI_TX2_DN_CON

4 4 7 7
EMC_HDMI@
HDMI_TX2_DP_CON 5 5 6 6 HDMI_TX2_DP_CON
RG3418 1 2 0_0402_5% @ HDMI_TX1_DN_CON

2
1
3 3 RPG1
2.2K_0404_4P2R_5%
8 +5VS_HDMI
RG3419 1 2 0_0402_5% @ HDMI_TX2_DP_CON JHDMI1

3
4
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ 18 15 DDPB_CLK_U
LG3403 +5V_Power SCL 16 DDPB_DATA_U
SDA
2

HDMI_TX2_DP_C 4 3
4 3 RG3420 HDMI_TX0_DP_CON 7
HDMI_TX0_DN_CON 9 TMDS_Data0+ 13
270_0402_1% TMDS_Data0- CEC
HDMI_TX2_DN_C 1 2 @ DG3403 HDMI_TX1_DP_CON 4 17
1 2 HDMI_DET 1 1 HDMI_DET HDMI_TX1_DN_CON 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI_DET
10 9 TMDS_Data1- Hot_Plug_Detect
1

EXC24CH900U_4P HDMI_TX2_DP_CON 1
DDPB_CLK_U 2 2 DDPB_CLK_U HDMI_TX2_DN_CON 3 TMDS_Data2+
EMC_HDMI@ 9 8 TMDS_Data2-
RG3421 1 2 0_0402_5% @ HDMI_TX2_DN_CON DDPB_DATA_U 4 4 7 7 DDPB_DATA_U 8 14
5 TMDS_Data0_Shield Utility
+5VS_HDMI 5 5 +5VS_HDMI 2 TMDS_Data1_Shield
6 6 TMDS_Data2_Shield
3 3 20
11 GND1 21
8 HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
RG3422 1 2 0_0402_5% @ HDMI_CLK_DP_CON TMDS_Clock- GND4
AZ1045-04F_DFN2510P10E-10-9
LG3404 EMC_NS@
2

HDMI_CLK_DP_C 4 3
4 3 ALLTO_C128AF-K1935-L
RG3423 For EMC
270_0402_1% ME@
HDMI_CLK_DN_C 1 2 @
1 2
1

A EXC24CH900U_4P A
EMC_HDMI@

RG3424 1 2 0_0402_5% @ HDMI_CLK_DN_CON

For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 34 of 60
5 4 3 2 1
 A B C D E F G H

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 35 of 60
A B C D E F G H
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HALL Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

M.2 SSD
+3VS +3VS_SSD

PJ3701
+3VS_SSD 1 2 Min 3A
JSSD1 1 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
JUMP_43X39

47U_6.3V_M_X5R_0603
1 2

CF3705

CF3706

CF3707

CF3708
3 GND_1 3.3V_1 4 @ 1 1 1 1 1 1

C4629
5 GND_2 3.3V_2 6

10U 6.3V M X5R 0402

CF3703
0.1U_6.3V_K_X5R_0201
1 1 C4630
9 PCIE_PRX_DTX_N5 PERN3 N/C_2 8
7 47U_6.3V_M_X5R_0603

CF3701
9 PCIE_PRX_DTX_P5 PERP3 N/C_3 10 2 2 2 2 2 2
9
PCIE_PTX_C_DRX_N5 GND_3 DAS/DSS# 12 @ @
0.22U_0402_10V6K 1 2 CF3702 11 @ @ @ @
9 PCIE_PTX_DRX_N5 PCIE_PTX_C_DRX_P5 PETN3 3.3V_3 14 2 2@
0.22U_0402_10V6K 1 2 CF3704 13
D 9 PCIE_PTX_DRX_P5 PETP3 3.3V_4 16 D
15
17 GND_4 3.3V_5 18
9 PCIE_PRX_DTX_N6 PERN2 3.3V_6 20
19
9 PCIE_PRX_DTX_P6 PERP2 N/C_4 22
21
0.22U_0402_10V6K 1 2 CF3709 PCIE_PTX_C_DRX_N6 23 GND_5 N/C_5 24
9 PCIE_PTX_DRX_N6 PCIE_PTX_C_DRX_P6 PETN2 N/C_6 26
0.22U_0402_10V6K 1 2 CF3710 25
9 PCIE_PTX_DRX_P6 PETP2 N/C_7 28
27
29 GND_6 N/C_8 30
9 PCIE_PRX_DTX_N7 PERN1 N/C_9 32
31
9 PCIE_PRX_DTX_P7 PERP1 N/C_10 34 +3VS_SSD
33
0.22U_0402_10V6K 1 2 CF3711 PCIE_PTX_C_DRX_N7 35 GND_7 N/C_11 36
9 PCIE_PTX_DRX_N7 PCIE_PTX_C_DRX_P7 PETN1 N/C_12 38
9 PCIE_PTX_DRX_P7 0.22U_0402_10V6K 1 2 CF3712 37
PETP1 DEVSLP 40

1
39
41 GND_8 N/C_13 42 +3VS_SSD RF3704
9 PCIE_PRX_DTX_P8 PERN0/SATA-B+ N/C_14 44 SSD_PCIE_DET#
43 100K_0402_5%
9 PCIE_PRX_DTX_N8 PERP0/SATA-B- N/C_15 46 SSD_PCIE_DET# 9
45 @
GND_9 N/C_16 48

1
0.22U_0402_10V6K 1 2 CF3713 PCIE_PTX_C_DRX_N8 47
9 PCIE_PTX_DRX_N8 PETN0/SATA-A- N/C_17 50

3
0.22U_0402_10V6K 1 2 CF3714 PCIE_PTX_C_DRX_P8 49 PLT_RST# RF3705 D
9 PCIE_PTX_DRX_P8 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ_Q# PLT_RST# 11,26,40,44
51 RF3703 1 2 0_0402_5% @ 100K_0402_5% 5 QF3701B
GND_10 CLKREQ# 54 SSD_CLKREQ# 10
53 @ G
10 CLK_PCIE_SSD# REFCLKN PEWAKE# 56

6
55 D 2N7002KDWH_SOT363-6
10 CLK_PCIE_SSD REFCLKP N/C_18 58

2
57 SSD_DET 2 S
GND_11 N/C_19

4
G @
59 NC NC 60
61 NC NC 62 QF3701A S

1
63 NC NC 64 +3VS_SSD 2N7002KDWH_SOT363-6
65 NC NC 66 @
67 68
SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72
73 GND_12 3.3V_8 74
SSD_DET#

CF3715
10U 6.3V M X5R 0402

CF3716
0.1U_6.3V_K_X5R_0201
1 1
75 GND_13 3.3V_9 SSD_DET RF3707 1 2 0_0402_5% @ SSD_PCIE_DET#
SATA-->GND 77
GND_14
76
PCIE-->NC PEG1 PEG2 2 2@

ARGOS_NASM0-S6701-TS40
C ME@ C

SATA

SATA_PTX_DRX_P0 CF3735 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX_P0_CON

9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 CF3736 1 SATA_PTX_DRX_N0_CON
9 SATA_PTX_DRX_N0
2 0.01U_6.3V_K_X7R_0201
+5VS +5VS_HDD
SATA_PRX_DTX_P0 CF3738 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX_P0_CON
9 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 CF3737 1 SATA_PRX_DTX_N0_CON
2 0.01U_6.3V_K_X7R_0201 PJ3708
9 SATA_PRX_DTX_N0
1 2
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39
@

CF3717

CF3718

CF3719
10U 6.3V M X5R 0402

CF3720
10U 6.3V M X5R 0402

CF3721
0.1U_6.3V_K_X5R_0201

CF3722 RF_NS@
33P_0402_50V8J

CF3723 RF_NS@
33P_0402_50V8J
1 1 1 1 1 1 1

2@ 2@ 2@ 2 2 2 2
SATA Redriver del 0526
B B

+5VS_HDD

JHDD1
1
2 1
3 2
4 3
SATA_PRX_DTX_P0_CON 5 4
SATA_PRX_DTX_N0_CON 6 5
7 6
SATA_PTX_DRX_N0_CON 8 7 12
SATA_PTX_DRX_P0_CON 9 8 GND2
10 9 11
A
10 GND1 A

HIGHS_FC5AF101-2931H
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 SATA HDD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor

+3VS

RS3901 1 2 10K_0402_5% SEN_THERM_N Near CPU core Near GPU&VRAM

RS3902 1 2 10K_0402_5% @ SEN_ALERT_N
REMOTE2+ REMOTE1+
D D
1

1
CS3902 C 1 C
+3VS 2 QS3902 CS3901 2 QS3901
100P_0402_50V8J B B
MMBT3904WH_SOT323-3 100P_0402_50V8J MMBT3904WH_SOT323-3
2 E E
2

3
1
CS3903 REMOTE2- REMOTE1-
0.1U_6.3V_K_X5R_0201
2 US3901 +3VALW +3VALW

1 10 EC_SMB_CK0
1 VCC SCL EC_SMB_CK0 26,44

1
CS3904
2200P_0402_50V7K REMOTE1+ 2 9 EC_SMB_DA0 RS3904 RS3903
DP1 SDA EC_SMB_DA0 26,44
13.7K_0402_1% @ 13.7K_0402_1%
2 REMOTE1- 3 8 SEN_ALERT_N @
DN1 ALERT#

2
REMOTE2+ 4 7 SEN_THERM_N NTC_V2 NTC_V1
DP2 THERM# NTC_V2 44 NTC_V1 44
1

1
CS3905 REMOTE2- 5 6
2200P_0402_50V7K DN2 GND RS3907 RS3906
100K_0402_1%_NCP15WF104F03RC @ 100K_0402_1%_NCP15WF104F03RC
2 F75303M_MSOP10 @

2
REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

C C

FAN Conn

+5VS
+5VS_FAN1 +5VS_FAN1
JFAN1
1
RS3909 1 2 0_0402_5% @ 44 EC_FAN_PWM 1
2
44 EC_FAN_SPEED 2
3
4 3
B 1 1 4 B
CS3907
CS3906 5
0.1U_6.3V_K_X5R_0201 GND1
10U 6.3V M X5R 0402 6
@ GND2
2 @ 2

HIGHS_WS33040-S0351-HF
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3V_WLAN
+3VALW_PCH

+3VALW RN4001 1 2 0_5%_0603 @

+3VALW
UN4001

1
RN4002 5 1 RN4003 1 @ 2 0.01_0603_1%
1
75K_0402_5% IN OUT 1
2

0.01U_0402_25V7K

100U_1206_6.3V6M
@
GND
1

1
WLAN_PWR_EN 4 3

CN4001

CN4002
EN OCB
SY6288C20AAC_SOT23-5
2@

2
1
D @

1
2 @
11 CNVI_EN# G QN4001

1
RN4004
RN4005 S 200K_0402_5%

3
75K_0402_5% @ @

2
@ L2N7002KWT1G_SOT323-3
2

+3V_WLAN
RN4006 1 @ 2 0_0402_5%
11 PM_SLP_WLAN#

1
RN4007 1 @ 2 0_0402_5%

CN4003
0.1U_6.3V_K_X5R_0201

CN4004
0.01U_0402_25V7K

CN4005
10U 6.3V M X5R 0402
44,43,46 SUSP#
RN4008 1 1 1
200K_0402_5%
@
@ @ @
2 2 2
2

NC if use SUSP#

JWLAN1
1 2
USB20_P10 3 GND1 3.3VAUX1 4
+3V_WLAN 9 USB20_P10 USB20_N10 USB_D+ 3.3VAUX2
5 6
9 USB20_N10 USB_D- LED1#
7 8
CNV_WR_D1N 9 GND2 PCM_CLK/I2S_SCK 10 CNVI_RF_RESET#_R RN4010 1 2 0_0402_5% @
10 CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 6
11 12
PCH_WLAN_OFF# 10 CNV_WR_D1P SDIO_CMD PCM_IN/I2S_SD_IN CNVI_MODEM_CLKREQ_R
RN4011 1 @ 2 10K_0402_5% 13 14 RN4012 1 2 0_0402_5% @
BT_OFF#_R CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 6
RN4009 1 2 10K_0402_5% 15 16
10 CNV_WR_D0N CNV_WR_D0P SDIO_DATA1 LED#2
2 17 18 2
10 CNV_WR_D0P SDIO_DATA2 GND11
19 20
+1.8VALW CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE# 22 CNVI_BRI_RSP_R RN4013 1 CNVI@ 2 1/20W_49.9_1%_0201
10 CNV_WR_CLKN CNV_WR_CLKP SDIO_WAKE# UART_RXD CNVI_BRI_RSP 10
23
10 CNV_WR_CLKP SDIO_RESET#
RN4014 1 @ 2 20K_0402_5% CNVI_BRI_DT

RN4015 1 2 100K_0402_5% CNVI_RGI_DT

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 CNVI_RGI_DT
PCIE_PTX_C_DRX_P9 GND3 UART_TXD CNVI_RGI_RSP_R RN4016 1 CNVI@ 2 1/20W_49.9_1%_0201 CNVI_RGI_DT 10
35 34
9 PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_N9 PETP0 UART_CTS CNVI_BRI_DT CNVI_RGI_RSP 10
37 36
9 PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD EC_TX CNVI_BRI_DT 10
39 38 RN4017 1 2 0_0402_5% @
PCIE_PRX_DTX_P9 41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD RN4018 1 2 0_0402_5% @ EC_RX
9 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 PERP0 VENDOR_DEFINED2
PCIE 43 42
9 PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
45 44
CLK_PCIE_WLAN 47 GND5 COEX3 46
+3V_WLAN 10 CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX2
49 48
+3VS 10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 RN4019 1 2 0_0402_5% @
WLAN_CLKREQ_Q# GND6 SUSCLK WLAN_PERST# SUSCLK 10
53 52
CLKREQ0# PERST0#
2

PCIE_WAKE#_WLAN 55 54 BT_OFF#_R RN4020 1 2 0_0402_5% @

PEWAKE0# W_DISABLE2# BT_OFF#
2

RN4021 57 56 WLAN_OFF# RN4022 1 2 0_0402_5% @

G

GND7 W_DISABLE1# PCH_WLAN_OFF# 8

QN4002 10K_0402_5%

@ CNV_WT_D1N 59 58 WLAN_SMB_DATA RN4023 1 2 0_0402_5% @

10 CNV_WT_D1N RSRVD/PETP1 I2C_DATA EC_RX 44
1

3 1 WLAN_CLKREQ_Q# CNV_WT_D1P 61 60 WLAN_SMB_CLK RN4024 1 2 0_0402_5% @

10 WLAN_CLKREQ# 10 CNV_WT_D1P RSRVD/PETN1 I2C_CLK EC_TX 44
63 62
S

GND8 ALERT#

1
L2N7002KWT1G_SOT323-3 CNV_WT_D0N 65 64 1
10 CNV_WT_D0N CNV_WT_D0P RSRVD/PERP1 RSRVD T4001
67 66 RN4026
10 CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#
RN4025 1 2 0_0402_5% @ 69 68 100K_0402_5%
CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1# 70
10 CNV_WT_CLKN CNV_WT_CLKP RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1#
73 72
10 CNV_WT_CLKP RSRVD/REFCLKN1 3.3VAUX3

2
75 74
GND10 3.3VAUX4
3 3
77 76
GND15 GND14
+3V_WLAN
ARGOS_NASE0-S6701-TS40
+3V_WLAN
PCIE_WAKE#_WLAN_R(GPP_H2) ME@ +1.8VALW

0.01U_0402_25V7K

0.1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

strap pin at PCH side, default internal 20K PD 1 1 1
1

CN4006

CN4007

CN4008
R3506 request by CNVi check list

1
RN4027
200K is to make sure GPP_H2 strap low at RSMRST# 200K_0402_5% RN30
GPP_H2 internal PD disabled after RSMRST# CNVI@ 2 2 2 @ 0_0201_5%
@
2

2
RN4028 1 @ 2 0_0402_5% PCIE_WAKE#_WLAN
11 PCIE_WAKE#

2
RN4032 1 2 0_0402_5% @
6 PCIE_WAKE#_WLAN_R
RN29
100K_0201_5%

1
2
QN3
RN4030 1 2 0_0402_5% @ WLAN_PERST#
11,26,37,44 PLT_RST# BT_OFF# 1 3
PCH_BT_OFF# [6]
RN4031 2 @ 1 0_0402_5%
8 PCH_WLAN_PERST#
LSI1012XT1G_SC-89-3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 40 of 60
A B C D E
 5 4 3 2 1

USB3.0 Port1 +USB_VCCA

+5VALW
UI4101
5 1
IN OUT
1
CI4101 2
1U_10V_M_X5R_0201 GND
4 3 USB_OC1#
2 ENB OCB USB_OC1# 4 +USB_VCCA +USB_VCCA
SY6288D20AAC_SOT23-5
JUSB2

41,44 USB_ON# USB30_TX_R_P2 9

Low Active 2A 1 StdA_SSTX+

100U_1206_6.3V6M

1U_0402_10V6K
USB30_TX_R_N2 8 VBUS

CI4103
D 1 StdA_SSTX- D
USB20_P1_R 3

CI4102
D+

2
7
USB20_N1_R 2 GND_DRAIN 10
2 @ USB30_RX_R_P2 6 D- GND_2 11
StdA_SSRX+ GND_3

1
RI4101 1 @ 2 0_0402_5% 4 12
USB30_RX_R_N2 5 GND_1 GND_4 13
StdA_SSRX- GND_5
LI4101
USB20_N1 4 3 USB20_N1_R
9 USB20_N1 4 3 ALLTO_C19043-10905-L
ME@
USB20_P1 1 2 USB20_P1_R
9 USB20_P1 1 2
EXC24CH900U_4P
EMC@

RI4104 1 @ 2 0_0402_5%

RI4105 1 2 0_0402_5% @

LI4102 +USB_VCCA USB20_P1_R

USB30_TX_P2 CI41041 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_P2 1 2 USB30_TX_R_P2 DI4102
9 USB30_TX_P2 1 2 USB20_N1_R
USB30_RX_R_N2 10 1 USB30_RX_R_N2
NC1 Line-1

1
USB30_TX_N2 CI41051 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N2 4 3 USB30_TX_R_N2
9 USB30_TX_N2 4 3 USB30_RX_R_P2 9 2 USB30_RX_R_P2

AZ5725-01F.R7GR_DFN1006P2X2

2
AZ5515-02FPR7GR_DFN1006P3X
DI4101 NC2 Line-2

1
EXC24CH900U_4P USB30_TX_R_N2 USB30_TX_R_N2
7 4
EMC_NS@ NC3 Line-3
EMC_NS@

EMC@

DI4105
USB30_TX_R_P2 6 5 USB30_TX_R_P2
NC4 Line-4
1 2 0_0402_5% @

2
RI4106
3
GND1

2
8

3
C GND2 C

RI4107 1 2 0_0402_5% @ AZ1143-04F-R7G_DFN2510P10E10

EMC@

LI4103
USB30_RX_P2 1 2 USB30_RX_R_P2
9 USB30_RX_P2 1 2
EMC
USB30_RX_N2 4 3 USB30_RX_R_N2
9 USB30_RX_N2 4 3
EXC24CH900U_4P
EMC_NS@

RI4108 1 2 0_0402_5% @

+5VALW +USB_VCCB
USB3.0 Port2 5
UI4301
1
IN OUT
1
CI4303 2 +USB_VCCB
GND +USB_VCCB
1U_10V_M_X5R_0201
4 3 USB_OC0#
2 ENB OCB USB_OC0# 9 JUSB1

100U_1206_6.3V6M
SY6288D20AAC_SOT23-5
USB30_TX_R_P1 9
41,44 USB_ON# 1

1U_0402_10V6K
StdA_SSTX+

2
1

CI4301

CI4302
USB30_TX_R_N1 8 VBUS
Low Active 2A USB20_P2_R 3 StdA_SSTX-
2 D+

1
7
USB20_N2_R 2 GND_DRAIN 10
B @ USB30_RX_R_P1 D- GND_2 B
6 11
4 StdA_SSRX+ GND_3 12
USB30_RX_R_N1 5 GND_1 GND_4 13
RI4301 1 @ 2 0_0402_5% StdA_SSRX- GND_5

ALLTO_C19043-10905-L
LI4301
USB20_N2 4 3 USB20_N2_R ME@
9 USB20_N2 4 3

USB20_P2 1 2 USB20_P2_R
9 USB20_P2 1 2
EXC24CH900U_4P
EMC@

RI4302 1 @ 2 0_0402_5%

DI4301
+USB_VCCB USB30_RX_R_N1 10 1 USB30_RX_R_N1 USB20_P2_R
NC1 Line-1
AZ5725-01F.R7GR_DFN1006P2X2

RI4303 1 2 0_0402_5% @ USB30_RX_R_P1 9 2 USB30_RX_R_P1 USB20_N2_R

NC2 Line-2
1

USB30_TX_R_N1 7 4 USB30_TX_R_N1

AZ5515-02FPR7GR_DFN1006P3X
NC3 Line-3

2
LI4302
1

USB30_TX_P1 CI4304 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_P1 1 2 USB30_TX_R_P1 USB30_TX_R_P1 6 5 USB30_TX_R_P1

EMC_NS@

DI4302

9 USB30_TX_P1 1 2 NC4 Line-4

3

EMC@

DI4509
USB30_TX_N1 CI4305 1 2 0.1U_6.3V_K_X5R_0201 USB30_TX_C_N1 4 3 USB30_TX_R_N1 GND1
9 USB30_TX_N1 4 3 8
2

EXC24CH900U_4P GND2
2

EMC_NS@ AZ1143-04F-R7G_DFN2510P10E10

3
EMC@
RI4304 1 2 0_0402_5% @

A RI4305 1 2 0_0402_5% @ A
EMC
LI4303
USB30_RX_P1 1 2 USB30_RX_R_P1
9 USB30_RX_P1 1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
9 USB30_RX_N1 4 3
EXC24CH900U_4P
EMC_NS@ Title
Security Classification LC Future Center Secret Data
1 2 0_0402_5% @
RI4306
Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 41 of 60
5 4 3 2 1
 A B C D E

USB2.0 PORT x1
+USB2_VCCA

+USB2_VCCA JUSB3
1
+5VALW +USB2_VCCA USB20_N4_R 2 VBUS
1
UI4302 USB20_P4_R 3 D- 1
5 1 4 D+ 5

100U_1206_6.3V6M
IN OUT GND GND1 6

470P_0402_50V7K
1 1 GND2
CI4306 2 7

CI4307

CI4308
GND 1 GND3
1U_10V_M_X5R_0201 8
4 3 USB_OC2# GND4
2 ENB OCB USB_OC2# 4 2 ALLTO_C107G1-10803-L
SY6288D20AAC_SOT23-5 2 ME@
@

USB_ON#
41,44 USB_ON# Low Active 2A

+5VALW

RI4307 2 @ 1 100K_0201_5% USB_ON#

USB20_N4_R

+USB2_VCCA USB20_P4_R

2
RI43081 @ 2 0_0402_5%

1
1
LI4304
USB20_P4 4 3 USB20_P4_R DI4306
9 USB20_P4 4 3 DI4305 AZC199-02S.R7G_SOT23-3

USB20_N4 1 2 USB20_N4_R

2
EMC@
9 USB20_N4 1 2

2
EXC24CH900U_4P AZ5725-01F.R7GR_DFN1006P2X2
EMC@ EMC_NS@

1
2 2
RI43091 @ 2 0_0402_5%

EMC

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 Port_Right & USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 42 of 60
A B C D E
 5 4 3 2 1

D D

Load Switch +3VS, C173 --> 2.74ms

+5VALW To +5VS +5VS, C176 --> 2.03ms
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
+5VS
+5VALW
Need Short
G2898KD1U_TDFN14P_2X3 J12 @
1 14 +5VS_LS 1 2
2 IN1_1 OUT1_2 13 1 2
IN1_2 OUT1_1 JUMP_43X79
1 1
C177 C3916 5VSON 3 12 C176 1 2 1 1
1U_0402_6.3V6K .01U_0402_16V7-K EN1 CT1 1000P_0201_50V7-K C174 C3917
EMC@ 4 11 0.1u_0201_10V6K 0.01U_0201_10V6K
2 2 +5VALW VBIAS GND @ EMC@
+3VALW 3VSON 5 10 C173 1 2 2 2
EN2 CT2 +3VS
2200P_0402_25V7-K
6 9 J11 @
7 IN2_1 OUT2_2 8 +3VS_LS 1 2
1 IN2_2 OUT2_1 1 2
C178
1U_0402_6.3V6K 15 JUMP_43X79

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
Thermal Pad
@ Need Short

C175

C4625

C4626
2 U13 1 1 1

@
2 2@ 2@
C C

@
SUSP# R64 1 2 0_0402_5% 3VSON
40,44,46 SUSP#

@
R27 1 2 0_0402_5% 5VSON
1 1
C180 C179
1U_0402_6.3V6K 1U_0402_6.3V6K
2 2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 3/5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

+3VL_EC +3VL_EC +3VL_EC_R

+3VL VCC_LPC_ESPI
1 @ 2 0_5%_0603 +1.8VALW

0.1U_6.3V_K_X5R_0201

1000P_50V_K_X7R_0201
1 1 +3VL +3VALW_PCH VCC_FSPI
RE4403 1 2 0_5%_0603 @ RE4402 RE4404 1 2 0_0402_5% @ +3VS

CE4407

CE4408

0.1U_6.3V_K_X5R_0201
1 2 0_0402_5% @

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 RE4405
2 2 EC_FAN_SPEED RE4409 1 2 100K_0402_5%

CE4409
1 1 1 1 1 1
RE4406 1 2 0_0402_5%

0.1U_6.3V_K_X5R_0201
@
CPU_VR_READY RE4410 1 2 10K_0402_5%

CE4401

CE4402

CE4403

CE4404

CE4405

CE4406
@ 1
RE4407 1 2 0_5%_0603 2

CE4410
2 2 2 2 2 2 RPE1
EC_SMB_DA0 1 4
2 EC_SMB_CK0 2 3
GPU/Thermal sensor
2.2K_0404_4P2R_5%
EC_AGND

+3VL_EC
D D

RPE2
EC_SMB_DA3 1 4
EC_SMB_CK3 2 3
PMIC
2.2K_0404_4P2R_5%

VCC_LPC_ESPI VCC_FSPI +3VL_EC RPE3

EC_SMB_CK1 1 4
EC_SMB_DA1 2 3
+3VL_EC_R Battery/Charger
2.2K_0404_4P2R_5%

UE4401
LID_SW#

106
114
121

127
RE4421 1 2 100K_0201_5%

11

74
26
50
92
IT8227E-CX_LQFP128_16X16
RE4415 1 EC_ESPI_IO0
2 0_0201_5% @ 10 87 EC_SMB_CK0 EC_ON_PCH RE4584 1 2 100K_0201_5%

VCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

AVCC
VFSPI
7 ESPI_IO0

VSTBY(PLL)
EC_ESPI_IO1 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 EC_SMB_DA0 EC_SMB_CK0 26,39
RE4416 1 2 0_0201_5% @ 9 88
GPU/Thermal sensor
7 ESPI_IO1 EC_ESPI_IO2 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 EC_SMB_CK1 EC_SMB_DA0 26,39 EC_USB_ON#
RE4417 1 2 0_0201_5% @ 8 SM BUS 115 RE4424 2 1 100K_0201_5%
7 ESPI_IO2 EC_ESPI_IO3 EIO2/LAD2/GPM2(3) SMCLK1/GPC1 EC_SMB_DA1 EC_SMB_CK1 52,53
RE4418 1 2 0_0201_5% @ 7 116
Battery/Charger
7 ESPI_IO3 EC_ESPI_RST# 22 EIO3/LAD3/GPM3(3) SMDAT1/GPC2 117 PECI_EC 2 1 43_5%_0201 EC_SMB_DA1 52,53
RE4438 ON/OFF RE4426 1 2 100K_0402_5%
EC_ESPI_CLK ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) ME_FLASH H_PECI 6
RE4419 1 2 0_0201_5% @ 13 118
7 ESPI_CLK EC_ESPI_CS# ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) ME_FLASH 6
RE4420 1 2 0_0201_5% @ 6 NOVO# RE4428 2 1 100K_0402_5%
7 ESPI_CS# ECS#/LFRAME#/GPM5(3)
EC_ON_3VALW_R RE4429 2 1 100K_0402_1%

PCH_ENBKL RE4423 1 @ 2 0_0402_5% EC_ENBKL 126

4,33 PCH_ENBKL 5 GA20/GPB5(3) 85 EC_ON_PCH
PLT_RST# 15 ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 86 PBTN_OUT# EC_ON_PCH 46
LPC RE4436 1 2 0_0201_5% @
11,26,37,40,44 PLT_RST# EC_SCI# 23 PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 89 EC_TP_INT# PBTN_OUT#_R 11
PS/2 RE4591 1 2 0_0201_5% @
6 EC_SCI# 14 ECSCI#/GPD3 PS2CLK2/GPF4 90 EC_BEEP PCH_TP_INT# 8,45
WRST#
VGA_AC_DET_EC WRST# PS2DAT2/GPF5 EC_BEEP

IT8227E-CX
RE4448 1 2 4 30
[26] VGA_AC_DET KBRST#/GPB6(3)
0_0201_5%
@ PWR_LED#
24

LQFP128
PWM0/GPA0 25 PWR_LED1# PWR_LED# 45 PWR_LED1 FP WHITE
PWM1/GPA1 28 BATT_LOW_LED# PWR_LED1# 30
EC_RTCRST#_ON 113 PWM2/GPA2 29 EC_USM BATT_LOW_LED# 45
ECLPM_BREAK_R CRX0/GPC0 PWM3/GPA3 EC_FAN_PWM EC_USM 54
RE4575 1 2 0_0201_5% @ 123 CIR 30
[8] ECLPM_BREAK CTX0/TMA0/GPB2(3) SMCLK5/PWM4/GPA4 31 PM_SLP_S4#_R RE4422 1 2 0_0201_5% @ EC_FAN_PWM 39
SMDAT5/PWM5/GPA5 PM_SLP_S4# 11

H_PROCHOT#_EC
PWM
80
RE4586 1 @ 2 0_0201_5% 119 DAC4/DCD0#/GPJ4(3) 47 EC_FAN_SPEED
55 VDDQ_PGOOD
RE4590 1 2 0_0201_5% @ 33 DSR0#/GPG6 TACH0A/GPD6(3) 48 FPR_PWR_EN_R RE4585 1 2 0_0201_5% @EC_FAN_SPEED 39
C [56] EC_ANS GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) FP_PWR_EN [45] C
GPG1:Def:GPO-L
RE4430 1 @ 2 0_0402_5% EC_VR_ON 81 120
11,26,37,44 PLT_RST# [56] EC_VR_ON DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) RESETN 45
124 SUSP#
1 2 0_0402_5% EC_ESPI_RST# EC_TX 17 TMRI1/GPC6(3) SUSP# 40,43,46
RE4432
7 ESPI_RST# 40 EC_TX EC_RX 16 TXD/SOUT0/LPCPD#/GPE6
@
40 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
+3VL_EC ADP_I 71 107 NOVO#
53 ADP_I 72 ADC5/DCD1#/GPI5(3) GPE4 18 PM_SLP_S3#_R 2 0_0201_5%NOVO# 30
UART port RE4444 1 @
73 ADC6/DSR1#/GPI6(3) WAKE UP RI1#/GPD0(3) 21 EC_USB_ON# PM_SLP_S3# 11
PSYS RE4443 1 2 0_0201_5% @
53,56 PSYS PCH_DPWROK_EC ADC7/CTS1#/GPI7(3) RI2#/GPD1 USB_ON# 41
RE4431 2 1 1K_0201_5% 35
11 PCH_DPWROK BATT_CHG_LED#_R RTS1#/GPE5
1

34 RE4437
[45] BATT_CHG_LED# SYS_PWROK 122 PWM7/RIG1#/GPA7 112 EC_ON_3VALW_R 1 2 0_0201_5% @ EC_ON
DE4401 RE4433
11 SYS_PWROK EC_SMB_DA3 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
54 when mirror, GPG2 pull high
RB521CM-30T2R_VMN2M-2 100K_0402_5% 95 110 ON/OFF when no mirror, GPG2 pull low +3VL_EC
55 EC_SMB_DA3 EC_SMB_CK3 94 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 111 GPIO_SCL_B4 1RE118 2 0_0201_5% @ ON/OFF 30,45
PMIC 55 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4
2

109 LID_SW# GPIO_SCL [45] GPG2 RE4434 1 2 100K_0402_5%

@ GPB1
2

RE4445 1 EC_SPI_CLK
2 1/20W_100_1%_0201 105 108 ACIN# LID_SW# 45
7 SPI_CLK EC_SPI_CS0# FSCK GPB0
WRST# RE4446 1 2 0_0201_5% @ 101 RE4435 1 @ 2 100K_0402_5%
26 WRST# 7 SPI_CS# EC_SPI_SI FSCE#
RE4447 1 2 1/20W_100_1%_0201 102
1U_6.3V_M_X5R_0201

WRST# MIN 10us

1 7 SPI_SI EC_SPI_SO FMOSI EXTERNAL SERIAL FLASH NTC_V1
RE4449 1 2 1/20W_100_1%_0201 103 66
CE4412

7 SPI_SO FMISO ADC0/GPI0(3) 67 PM_SLP_S0#_R RE4425 1 2 0_0201_5% @ NTC_V1 39

56 ADC1/GPI1(3) 68 NTC_V2 PM_SLP_S0# 11,43
KSO16
2 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 PM_SLP_SUS#_R RE4427 1 2 0_0201_5% @ NTC_V2 39
KSO17
EC_VPP_PWREN 32 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 70 CPU_VR_READY PM_SLP_SUS# 11
[55] EC_VPP_PWREN PWM6/SSCK/GPA6 ADC4/GPI4(3) CPU_VR_READY [56]
GPG0:Def:GPO-H GPG2 100 A/D D/A
125 SSCE0#/GPG2
SSCE1#/GPG0 SPI ENABLE EC_VCCST_PWRGD
76
KSO0 36 TACH2A/GPJ0 77 EC_MUTE# EC_VCCST_PWRGD 11
37 KSO0/PD0 TACH2B/GPJ1 78 EC_TP_ON EC_MUTE# 30
KSO1
KSO2 38 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 79 BKOFF# EC_TP_ON 45
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) BKOFF# 33
KSO4 40 KSO3/PD3 EC_VCCST_EN RE4440 1 @ 2 100K_0402_5%
KSO5 41 KSO4/PD4
KSO6 42 KSO5/PD5 SUSP# RE4441 1 2 100K_0402_5%
KSO7 43 KSO6/PD6
KSO8 44 KSO7/PD7 BKOFF# RE4442 1 2 10K_0402_5%
KSI[0..7] KSO9 45 KSO8/ACK#
45 KSI[0..7] KSO10 46 KSO9/BUSY
KSO[0..17] KSO11 51 KSO10/PE 2 BATT_TEMP EC_ON_1.8V RE4580 1 2 100K_0201_5%
45 KSO[0..17] 52 KSO11/ERR# GPJ7 128 AC_PRESENT BATT_TEMP 52,53
KSO12 CLOCK RE4450 1 2 0_0201_5% @
53 KSO12/SLCT GPJ6 AC_PRESENT_R 11 EC_VPP_PWREN
KSO13 RE4581 1 2 100K_0201_5%
KSO14 54 KSO13
KSO15 55 KSO14 84 RE4528 1 EC_VCCST_EN
2 0_0201_5%
KSO15 KBMX EGCLK/GPE3
@
EC_VCCST_EN [46]
83
EGCS#/GPE2 82 GPIO_AL0 45 EC_USM
B RE4583 1 2 100K_0201_5% B
KSI0 58 EGAD/GPE1
KSI1 59 KSI0/STB#
KSI2 60 KSI1/AFD# 19
KSI3 61 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0 20 GPIO_AL0 RE4587 2 1 1/20W_49.9K_1%_0201
KSI4 62 KSI3/SLIN# SMDAT4/L80LLAT/GPE7
KSI4 GPIO EC_SMI_R PWR_LED1#
KSI5 63 3 RE4579 1 @ 2 0_0201_5% RE4588 1 2 100K_0201_5%
64 KSI5 GPH7 99 PCH_PWROK EC_SMI 6
KSI6 PCH_PWROK 11
KSI7 65 KSI6 ID6/GPH6 98 PWR_LED2# PWR_LED2# RE4589 1 2 100K_0201_5% @
KSI7 ID5/GPH5 97 PWR_LED2# 30 PWR_LED2 FP AMBER
ID4/GPH4 EC_ON_1.8V DELINK 45
96
VCORE

ID3/GPH3 93 EC_RSMRST#_EC RE4452 1 2 1K_0201_5% EC_ON_1.8V 55

AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0 EC_RSMRST# 11
1
27
49
91
104

75

12

SA0000A8N00

CE4411 Emergency Power Loss Early De-assertion of DSW_PWROK control circuit

VCOREVCC 2 1
RE4453 1 @ 2 0_0402_5% ALW_PWRGD DE4402 1 2 EC_RSMRST#
54 +3VALW_PG
EC_AGND 0.1U_6.3V_K_X5R_0201
RB521CM-30T2R_VMN2M-2

RE4454 1 2 0_0402_5% @ DE4403 1 2 PCH_DPWROK

54,55 +5VALW_PG
RB521CM-30T2R_VMN2M-2

CPU_VR_READY CE4413 1 2 EMC_NS@ 0.1U_6.3V_K_X5R_0201

VDDQ_PGOOD CE4414 1 2 EMC_NS@ 0.01U_6.3V_K_X7R_0201

PM_SLP_S4# CE4415 1 2 EMC_NS@ 1000P_0201_50V7-K

+3VL
EC_RTC_RST# 10 PM_SLP_S3#
RE4455 1 2 0_0402_5% @ H_PROCHOT# 6,13,55 CE4416 1 2 EMC_NS@ 1000P_0201_50V7-K
53,56 VR_HOT#
1

Power side install NOVO# CE4417 1 2 0.1U_6.3V_K_X5R_0201

1

RE4456 1 QE4401
100K_0402_5% RE4457 CE4418 SSM3K15AMFV_2-1L1B PECI_EC CE4419 1 2 EMC_NS@ 47P_0201_25V8-J
100_0402_5% 47P_0201_25V8-J EC_RTCRST#_ON 2
EMC_NS@ BATT_TEMP CE4420 1 2 EMC_NS@ 100P_0201_25V8J
2

2
1

ACIN# RE4458 1 2 0_0402_5% @

1 2

RE4459 ACIN# CE4421 1 2 EMC_NS@ 100P_0201_25V8J

1

A 10K_0402_5% A
QE4402 ON/OFF CE4422 1 2 EMC_NS@ 1U_6.3V_M_X5R_0201
2

2 H_PROCHOT#_EC 2 PLT_RST# CE4423 1 2 EMC_NS@ 220P_0201_25V7-K

ACIN 53
QE4403
SSM3K15AMFV_2-1L1B SSM3K15AMFV_2-1L1B
3

@ For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2017/09/01 Deciphered Date 2017/09/01 EC ITE8586LQFP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

RI4629 1 2 0_0402_5% @
K/B Connector +3VS
PWR_CAPS_LED
RI4501 1 @ 2 0_0402_5% 32
JKB1
33
+3VALW CAPS_LED# RI4502
CAPS_LED#_R 32 GND1
1 2 200_0402_1% 31 34
8 CAPS_LED# 31 GND2
KSO15 30
KSO10 29 30
KSO11 28 29
KSI[0..7] KSO14 27 28
KSI[0..7] 44 27
KSO13 26
KSO[0..17] KSO12 25 26
KSO[0..17] 44 25
KSO3 24
KSO6 23 24
KSO8 22 23
KSO7 21 22
KSO4 20 21
ON/OFF RI4503 1 2 0_0402_5% @ ON/OFFBTN# KSO2 19 20
30,44 ON/OFF 19
KSI0 18
KSO1 17 18
D
J4501 J4502 KSO5 16 17 D
1 16

2
CI4501 KSI3 15
0.1U_6.3V_K_X5R_0201 SHORT PADS SHORT PADS KSI2 14 15
@ @ @ KSO0 13 14
2 13

1
KSI5 12
KSI4 11 12
KSO9 10 11
KSI6
KSI7
9
8
10
9
TP/B Connector
KSI1 7 8
KSO16 6 7 JTP1 JTP2
KSO17 5 6 RI4507 1 2 0_0402_5% @ EC_TP_ON_R 1 EC_TP_ON_R 1
NUM_LED#_R 5 44 EC_TP_ON TP_INT# 1 TP_INT# 1
RI4504 1 1517@ 2 200_0402_1% 4 RI4508 1 2 0_0402_5% @ 2 2
8 NUM_LED# PWR_LED# 4 8,44 PCH_TP_INT# 2 2
RI4505 1 S145@ 2 200_0402_1% 3 3 3
ON/OFFBTN# RI4627 1 S145@ 2 0_0201_5% 2 3 PCH_I2C1_SDA_TP 4 3 4 3
2 8 PCH_I2C1_SDA_TP PCH_I2C1_SCL_TP 4 4
RI4628 1 S145@ 2 0_0201_5% 1 5 5
1 8 PCH_I2C1_SCL_TP 5 PCH_I2C1_SDA_TP 5
1 1 6 6
TP_PWR 6 PCH_I2C1_SCL_TP 6
HIGHS_FC8AR321-3160-1H 7
CI4507 7
KSO15 RI4623 1 S350@ 2 0_0201_5% KSO15_R ME@ CI4506 100P_0402_50V8J 7
TP_PWR
8
KSI1 RI4624 1 S350@ 2 0_0201_5% KSI1_R 100P_0402_50V8J EMC_NS@ 8 GND1 8
EMC_NS@ 2 2 GND2 9
HIGHS_FC5AF061-2931H 10 GND1
ME@ GND2
HIGHS_FC5AF081-2931H
ME@
CAPS_LED#_R NUM_LED#_R PWR_LED# ON/OFFBTN# PWR_CAPS_LED

+3VS TP_PWR PCH_I2C1_SCL_TP

AZ5123-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
PCH_I2C1_SDA_TP

AZ5123-01F.R7GR_DFN1006P2X2
1
RI4506 1 2 0_0402_5% @
1

3
100P_0402_50V8J

100P_0402_50V8J
EMC@

DI4504
2

1
1517@
EMC@

EMC_NS@

EMC_15_NS@
100P_0201_25V8J

EMC_NS@

EMC_NS@

CI4505
2 2 DI4505
1

1
DI4501

CI4503

CI4504

DI4503

1
DI4502

CI4502 EMC_NS@
1 0.1U_6.3V_K_X5R_0201
1 1
2 2
2

C C
2

AZC199-02S.R7G_SOT23-3

1
For EMC

+3VS_FP
44 BATT_LOW_LED#
BATT_LOW_LED# LED1 1 2 RI45091 2 470_0402_5% +3VALW Finger Print Connector

1
L-C192JFCT-LCFC_SUPER_AMBER
1

RI4622
FP@ 330_0402_1%
1

D4501
AZ5123-01F.R7GR_DFN1006P2X2

1 2
EMC_NS@ +3VL +3VS_FP
+3VL QI4501
2

LP2301ALT1G_SOT23-3
FP@
2

1
FP_PWR_EN# 2 QI4502
1
RI3803 3 1 CI4508

D
1/20W_200K_5%_0201 1 0.1u_0201_10V6K SSM3K15AMFV_2-1L1B

3
BATT_CHG_LED# LED2 1 2 RI45101 2 470_0402_5% FP@ CI4510 FP@ FP@
44 BATT_CHG_LED# +3VALW 1 2
0.047U_0402_25V_X7R_0402 CI4511

G
2

2
L-C192WDT-LCFC_WHITE FP@ 0.1u_0201_10V6K
2
1

RI4525 1 2 0_0201_5% @ @
2 +3VS_FP
1

1
0_0201_5% 1 @ 2 RI4619 FP_PWR_EN
D4502
RI4621 RI4521 2 @ 1 1/20W_4.7K_5%_0201 GPIO_AL0
AZ5725-01F.R7GR_DFN1006P2X2
100K_0201_5%
EMC_NS@
FP@ 1 RI4522 2 @ 1 1/20W_4.7K_5%_0201 GPIO_SCL
CI4509
2

2
FP_PWR_EN# 0.1u_0201_10V6K RI4523 2 1 1/20W_4.7K_5%_0201 FPR_RESET
2

B B
@
2

1
QI3802 @
FPR_RESET RI4524 1 @ 2 1/20W_4.7K_5%_0201
2
PWR_LED# 44 FP_PWR_EN DELINK_R
44 PWR_LED# LED3 1 2 RI45111 2 470_0402_5% +3VALW RI4618 1 @ 2 100K_0201_5%

1
SSM3K15AMFV_2-1L1B

100K_0201_5%

3
L-C192WDT-LCFC_WHITE FP@

RI3806
1

FP@
1

2
D4503
AZ5725-01F.R7GR_DFN1006P2X2 +3VS_FP JFP1
EMC_NS@ 10
9 GND2
2

GND1
2

RI4513 1 2 0_0402_5% @ 8
USB20_N7_CONN 7 8
LI4501 USB20_P7_CONN 6 7
USB20_N7 1 2 USB20_N7_CONN RI4620 1 @ 2 0_0201_5% 5 6
9 USB20_N7 1 2 8 FPR_DELINK 5
DELINK RI4515 1 2 0_0201_5% @ DELINK_R 4
44 DELINK GPIO_AL0 RI4516 4
1 2 0_0201_5% @ GPIO_AL0_R 3
USB20_P7 USB20_P7_CONN 44 GPIO_AL0 FPR_RESET 3
4 3 RESETN RI4517 1 @ 2 0_0201_5% 2
9 USB20_P7 4 3 44 RESETN 2
1
HALL Sensor EXC24CH900U_4P
EMC_NS@
44
8 FPR_RESET
GPIO_SCL
GPIO_SCL RI4518 1 2 0_0201_5% @ GPIO_SCL_R 1
HIGHS_FC5AF081-2931H
ME@
RI4514 1 2 0_0402_5% @
+3VL
US4501 USB20_N7_CONN +3VS_FP
@
RS4501 1 2 0_0402_5% +VCC_LID 2

AZ5515-02FPR7GR_DFN1006P3X

AZ5725-01F.R7GR_DFN1006P2X2
DI4508
VCC DELINK_R 10 1 DELINK_R USB20_P7_CONN
2 NC1 Line-1
CS4501 3 RS4502 1 @ 2 0_0402_5% LID_SW# GPIO_AL0_R 9 2 GPIO_AL0_R
OUTPUT LID_SW# 44 NC2 Line-2

1
.01U_0402_16V7-K
1 1 FPR_RESET 7 4 FPR_RESET

EMC_FP@

EMC_NS@
@ 2

1
GND CS4502 NC3 Line-3

DI4506

DI4507
A A
AH9247-W-7_SC59-3 100P_0402_50V8J GPIO_SCL_R 6 5 GPIO_SCL_R
EMC_NS@ NC4 Line-4
1 3
GND1

2
8
GND2

2
AZ1143-04F-R7G_DFN2510P10E10
EMC_FP@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/TP_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
DocumentNumber
Number Rev
Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 45 of 60
5 4 3 2 1
 A B C D E

+3VALW to PCH

+3VALW

PJ4602
1 2@
1 2 +3VALW_PCH
1
CX4601 JUMP_43X39
1U_6.3V_M_X5R_0201 UX4608
1 14 +3VPCH_LS
2 2 IN1_1 OUT1_2 13
IN1_2 OUT1_1 1
CX4607
3 12 CX46221 2 1000P_50V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
1 44 EC_ON_PCH EN1 CT1 1
VBIAS 4 11 2
VBIAS GND

0.01U_0402_25V7K
C4624
1
5 10 CX4623 1 2 1000P_50V_K_X7R_0201
EN2 CT2 UX4711

1
@ 6 9 @ VCCSTG_EN_A 1 4 VCCSTG_EN_B
2 RX4633 7 IN2_1 OUT2_2 8 VCCIN_AUX_VALID 2 IN B OUT Y
IN2_2 OUT2_1 IN A
0_0201_5%
@ 15 3 5
Thermal Pad GND Vcc

2
TPS22976DPUR_WSON_2X3
MC74VHC1G32DFT2G_SC70-5
@ +3VALW
OR Gate

+5VALW RX4632 1 2 0_0201_5% VBIAS 1

C4627
@ 0.1U_6.3V_K_X5R_0201
2

+1.8VALW to +1.8VS
+1.8VALW +1.8VS
+3VS
RX4601 1 @ 2 1/2W_0.01_+-1%_0603_50PPM/C +5VL

1
QX4601 0.6A

1
3 1 LP2301ALT1G_SOT23-3 R3120
S

RX4630 100K_0201_5%
0.1U_6.3V_K_X5R_0201

2 100K_0402_5% @ 2
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CX4602

RX4603
10K_0402_5%

G
2

2
2

CX4603

CX4604

CX4605

1 1 1 1

2
SUSP R3121 1 @ 2 0_0201_5%
SUSP 34 [11,44] PM_SLP_S0#
UX4712
R3122 1 2 0_0402_5% @ 1 4 VCCSTG_EN_A
2 2 2 2 [11] CPU_C10_GATE# IN B OUT Y

1
D EC_VCCST_EN RX4740 1 @ 2 0_0201_5% 2
@

[44] EC_VCCST_EN IN A
1

@ @ 2
40,43,44 SUSP#
@ G QX4606 3 5
SUSP RX4604 1 2 0_0402_5% 3V3_VCCST_OVERRIDERX4741 1 2 0_0402_5% GND Vcc
L2N7002KWT1G_SOT323-3 SLP_S3#
S

3
1

1 @ MC74VHC1G32DFT2G_SC70-5
CX4609
RX4606 +3VALW
0.1U_6.3V_K_X5R_0201
470K_0402_5% OR Gate
@
2
2

1
+3VALW +VCC1.05_OUT_FET
C4628
0.1U_6.3V_K_X5R_0201
2
1 1
CX4719 CX4720
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
2 2

+VCCSTG_CPU_LS
UX4713 150mA
2 4 RX4742 1 2 0_0402_5% @ +VCCSTG_CPU
VIN VOUT
VCCST&VCCSTG 5
VBIAS NC
3
VCCSTG_EN_A RX4743 1 VCCSTG_EN
2 0_0402_5% @ 6 1
+3VALW +3VALW ON GND
VCCSTG_EN_B RX4744 1 2 0_0201_5% EM5201BJ-45_SOT23-6
@
2

3 3
RX4619 RX4618

1
100K_0201_5% 100K_0201_5%
RX4745
UX4605 @ 200K_0402_5%
1

3V3_VCCST_OVERRIDE 1 4 PM_SLP_VCCST_OVRD1 2 0_0201_5%

@ @ IN B OUT Y
2 RX4622
PM_SLP_VCCST_OVRD_R

IN A

2
3 5
GND Vcc +3VALW
6

CX4619
D1

D2

2 5 MC74VHC1G32DFT2G_SC70-5
11 VCCST_OVERRIDE G1 G2
1

2 1 +VCC1.05_OUT_FET
@
RX4625
S1

S2

OR Gate 200K_0402_5%
QX4602A QX4602B 0.1U_6.3V_K_X5R_0201 @ 1
1

PJT7838_SOT363-6 PJT7838_SOT363-6 @ CX4618

2

+3VALW 10U 6.3V M X5R 0402

+VCCST_CPU_LS +VCCST_CPU
@ @ 2
RX4746 1 2 0_0201_5% @
1
EC_VCCST_EN RX4621 1 2 0_0201_5% +VCCST_EN UX4606 UX4604
44 EC_VCCST_EN VCCST_EN_R
1 4 CX4617 2 4 RX4620 1 2 0_0402_5% @
2 IN B OUT Y 1U_6.3V_M_X5R_0201 VIN VOUT
IN A 2 5 3
3 5 VBIAS NC If VCCST is enabled by SLP_S4#, no power
GND Vcc RX4624 1 2 0_0201_5% @ VCCST_EN 6 1 gate is required for VCCPLL_OC and it can
ON GND be merged with VDDQ directly.
CX4620 +3VALW If VCCST is enabled by SLP_S3#, a power
MC74VHC1G32DFT2G_SC70-5 EM5201BJ-45_SOT23-6 gate is required for VCCPLL_OC.
UX4607 RX4628 OR Gate 2 1
1 4 VCCIN_AUX_VALID 1 2 VCCIN_AUX_VCCST_R
55,13 VCCIN_AUX_VID0 IN B OUT Y
2 0.1U_6.3V_K_X5R_0201 1 @ 2 0_0201_5%
55,13 VCCIN_AUX_VID1 IN A
1

0_0201_5%

1
3 5 @ RX4623
GND Vcc +3VALW
RX4629
CX4621
@ 200K_0402_5% RX4627
2 1
MC74VHC1G32DFT2G_SC70-5 @ 200K_0402_5%
2

OR Gate PM_SLP_VCCST_OVRD

2
4 4
0.1U_6.3V_K_X5R_0201
@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20

DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 46 of 60
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN
A2 A4 B5

V V
3 +3V_PCH
PU301 PU904

V
B+
BATT BATT V +3VALW
1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU
A3 B4

V V
PM_SLP_S5#
PM_SLP_SUS# 6
CPU_PLTRST# 16

V
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE
+1.35V

V
11 VR_REDY SYSON 7 PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)
+1.5VS_VGA

V
PU901 VR_ON Q31

V
V

+CPU_CORE PU601

V
+5VS

B B
Q32 +1.05VSP_VGA

V
V
SUSP#,SUSP 9 +3VS PU702
VGA

V
PU602

V
+1.5VS +3VS_VGA

V
Q27
PU502

V
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD

FD4901 FD4902 FD4903 FD4904 FD4905 FD4906

1
D
MD Shielding D

CPU Thermal Hole SH4901 SH4902 SH4903 SH4904 SH4905 SH4906

H4902 H4904 H4906 H4907

HOLEA HOLEA HOLEA HOLEA
1

1
1

1
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

GPU Thermal Hole

C
H4903 H4905 C
HOLEA HOLEA
1

PAD_CT6P0B7P0D3P2 PAD_CT6P0B7P0D3P2
SODIMM Shielding

SH4911
SH4907 SH4908 SH4909 SH4910

H4908 H4909 H4910 H4911

HOLEA HOLEA HOLEA HOLEA

1
1

1
B B
PAD_C7P0D4P0 PAD_C7P0D4P0 PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N

H4912 H4913 H4914 H4901 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

HOLEA HOLEA HOLEA HOLEA
1

PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C10P0D8P0

H4915 H4916 H4917

HOLEA HOLEA HOLEA
1

A A
PAD_C7P0D2P4 PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HS45A/HS55A 0.1

Date: Monday, November 02, 2020 Sheet 49 of 60

5 4 3 2 1
 5 4 3 2 1

V9B+
+3.3V/6A
Silergy
SY8386B
Adaptor 65W Converter
D
EN D

FOR 3VALW PGOOD

+5V/8A
Richtek VCCIN_AUX/14A

RT6258C
EN Converter
FOR 5VALW PGOOD +1.8VALW/4A

TI Richtek +1.35V/8A Silergy +2.5V/1A

BQ24780SRUYR LV5095B LV5116A

Battery Charger Switch Mode SYS PMIC
EN
C C

Switch Mode FOR VRAM PGOOD

+1.2V/8A

+0.6VS/1A
Richtek
SMBus RT8816C +VGA_CORE/35A

EN Switch Mode
PGOOD
FOR GPU VDDC

Battery Richtek
polymer RT3613EE VCCIN/43A

2S1P Switch Mode

EN FOR CPU Core
PGOOD
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

PJ5101 @ PJ5102 @
JUMP_43X79 JUMP_43X79
1
1 2
2 1
1 2
2
VIN
3.25A HCB2012KF-121T50_0805
JDCIN1 PF5101 PL5101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 EMC@
3 7A_24VDC_F1206HI7000V024TM
GND2 4
@

1000P_0201_50V7-K
470P_0201_50V7-K
GND3 5 HCB2012KF-121T50_0805

1000P_0201_50V7-K

470P_0201_50V7-K
GND4

EMC@

EMC@
6 PL5102

PC5101

PC5102
GND5

2
EMC@

EMC@
D 7 1 2 D

PC5103

PC5104
GND6
EMC_NS@
HIGHS_PJSS0026-8B01H

1
ME@

change symbol to DC021508142 by amy 0704

+3VL

2
PR5101
@ 0_0402_5%

VCCRTC 1
1

PR5102
C 45.3K_0402_1% C
@ RTC_VCC
2

1
JRTC1
3 2 PR5103 1 1
2 1
PD5101 1K_0603_5% 3 2
GND1
2

BAT54CW_SOT323-3 4
PC5105 GND2
1U_0402_6.3V6K
1

HIGHS_WS33020-S0351-HF
@ ME@

change symbol to SP021510283 by amy 0620

RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-DCIN / RTC charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D
JBATT1 10A HCB2012KF-121T50_0805
BATT+
D

1 PL5201
1 2 1 2
9 2 3 EC_SMCA PR5201 1 2100_0402_1%
10 GND1
GND2
3
4
4 EC_SMDA 1 2
EC_SMB_CK1
EC_SMB_DA1
44,53
44,53 1 2 2S1P polymer battery
5
5
6
PR5202 100_0402_1%
PL5202 voltage level: +5.5V ~
6
7
7 HCB2012KF-121T50_0805
8.8 V

3
8 EMC@
8

1
PC5201 PC5202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
VBAT
JBATT2
PD5201
AZC199-02S.R7G_SOT23-3
1
1 2 EMC_NS@

1
2 3 EC_SMCA
9 3 4 EC_SMDA
10 GND1 4 5
GND2 5 6
6 7
7 8
8 PR5203
1 2 +3VALW
100K_0402_1%
HIGHSTAR_WS33081-S120S-1H
C C
ME@ PR5204
1 2
BATT_TEMP 44,53
10K_0402_5%

1
1

PD5202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
PQ100 PQ101
AONS32314_DFN8-5 AONR32340C_DFN8-5 N2
N1 PR100
1 1 0.01_1206_1%
2 2 S1 5 V9B+
5 3 3 S2 D 1 4
S3

G
2 3
D D

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K
470P_0201_50V7-K

4700P_0402_50V7-K

6800P_0402_25V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

0.01U_0201_25V6-K
0.022U_0402_25V7K
4

EMC_NS@

EMC_NS@
PC100
2 2

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC102

PC103

PC104

PC105

PC106

PC107

PC108

PC109
1

PC101
PR101
1 1

2
4.7_0603_5%

5
0.1U_0201_25V6-K

2
PQ102
PC110
AON6324_DFN8-5
1 2
@
BQ24780_BATDRV 1 2 BQ24780_BATDRV_R 4

2
09/09 NC MEC part
PC111 PC112 PR102
0.1U_0201_25V6-K 0.1U_0201_25V6-K 0_0402_5%

3
2
1
2
PR103
499K_0402_1% PC113
0.01U_0201_25V6-K

1
VIN BATT+

2
BAT54CW_SOT323-3
PD100
2

3
V9B+
VIN
4.02K_0603_1%

1
1

1
4.02K_0603_1%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
EMC_NS@
ACN
ACP
PR105

PR106

1
PC114

PC115

PC116
10_1206_5%
2
1
BQ24780_VDD

PR104
2

2
2

5
C PR107 PU100 C
7.15K_0402_1% 44.2K_0402_1%

ACN
ACP
PC117 PC118
1 2

1
PR108 2 1 780_VCC 28 24 1 2
VCC REGN

2
PQ103
1 2 ACDET 6 4
PC119 0.47U_0402_25V6K ACDET 2.2U_10V_K_X5R_0402
PR109 PC120 AON7380_DFN8-5
0.01U_0402_25V7K 25 BST_CHG 1 2 1 2
BTST PR110
2.2_0603_5% PL100 0.01_1206_1% 6A
.047U_0402_16V_X7R_0402
BATT+

3
2
1
3 26 DH_CHG 2.2UH_PCMB063T-2R2MS_8A_20%
CMSRC HIDRV 1 2 CHG 1 4
@

5
PR111 2 1 20K_0402_1% 4
ACDRV

1
@ 2 3
PR112 2 1100K_0402_1% 27 LX_CHG PR113
BQ24780_VDD PHASE

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
@ 2.2_0805_5%

1
PR114 1 2 0_0402_5% ACIN_R 5 PQ104 EMC_NS@

PC122

PC121

PC123

PC124
44 ACIN @ ACOK 4

2
PR115 1 2 0_0402_5% EC_SMB_DA1_R 11 AON7380_DFN8-5
SDA

2
44,52 EC_SMB_DA1 23 DL_CHG

470P_0201_25V7K
LODRV

1
@

2
PR116 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC126

PC125
SCL GND

3
2
1
44,52 EC_SMB_CK1 1000P_0402_50V7K

2
@ BQ24780SRUYR_QFN28_4X4 EMC_NS@

1
PR117 1 2 0_0402_5% ADP_I_R 7 29
44 ADP_I IADP PAD @

0.1U_0201_25V6-K

0.1U_0201_25V6-K
2

2
IDCHG 8 18 BQ24780_BATDRV

PC127

PC128
IDCHG BATDRV
9 PR118 10_0603_5%
PMON

1
44,56 PSYS 17 2 1
BATSRC
20K_0402_1%
100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J
2

PR121 @ 20 SRP_R 2 1 SRP

SRP

0.1U_0201_25V6-K
2

1 2 0_0402_5% 10 PR120 10_0603_5%

PR119

PC131

44,56 VR_HOT# PROCHOT#

PC129

2
PC130

PC132
1

13
CMPIN
1

BATPRES#
1

1
TB_STAT#
14
CMPOUT 19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR122 10_0603_5% B
ILIM
2

16

15
PR123
0_0402_5% @
09/19 PR331 change from 147K to 133K
PR124 PR125
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
30K_0402_1%
133K_0402_1%
0.01U_0201_25V6-K

1
2

PC133

PR126
100K_0402_1%
1

ACDECT setting 17.2V

Charge current limit HW=7A
DC discharge limit =26A
Discharge current limit HW=9A during Turbo boost

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 53 of 60
5 4 3 2 1
 A B C D

+3VALW

1
PR5917
100K_0402_5%

2
PU5901
@
PJ5901 PR5909
2 1 +3VALW_VIN 2 7 +3VALW_PWRGD 2 1 +3VALW_PG [44]
V9B+ 2 1 IN1 PG
6A

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
3 1 +3VALW_BST 1 2
1 1 IN2 BS

0.01U_0402_25V7K
1
JUMP_43X79 4 PC5902 0_0402_5% @
IN3

SY8386BRHC_QFN16_2P5X2P5
@ 0.1U_0603_25V7-M

PC5903

PC5901

PC5904
5 PL5901
2 2 LX1 PJ5902

2
6 15 2.2UH_PCMB063T-2R2MS_8A_20%
14 GND1 LX2 16 +3VALW_LX 1 2 +3VALW_P 1 2
17 GND2 LX3 1 2 +3VALW
GND3

1
1 1

EMC_NS@ PR5902 JUMP_43X118

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 2 0_0402_5% +3VALW_EN1 9 11 +3VALW_P 2.2_0805_5%
EN1 OUT @

1
[44] EC_ON +3VALW_VIN 1 2+3VALW_EN2 8 EMC_NS@
PR5901 PR5907 EN2 10 +3VALW_FF

PC5905

PC5906

PC5907

PC5908

PC5913

PC5914
FF

1 2
@ +3VALW_SN
10K_0402_1%

2
12
TEST 100mA

0.1U_0402_10V7K
1

1
13
+3VLP
PC5910
Vout=3.3V+-5%

1M_0402_5%
LDO

1
1000P_0402_50V7K

PC5909

PR5903

1M_0402_5%
Vset=3.338V typ

2
EMC_NS@ @ @

PR5904
1

2
FSW=600KHz typ
1

PR5906 PC5911 PC5912 PR5905

2
2
4.7U_0402_6.3V6M 1000P_0402_25V7-K 1K_0402_1%
OCP=8A typ

2
68K_0402_1% 1 2 +3VALW_FF_R 1 2
OVP=Vout*120% typ
UVP=Vout*60% typ
2

PJ5903 @
+3VALW_USM_R 2 1
+3VLP 2 1 +3VL
USM mode: 1V <EN1<1.6V JUMP_43X39
1

PFM mode: 2V <EN1

2
[44] EC_USM SSM3K15AMFV_2-1L1B
1

PR5908 PQ5901
100K_0402_5% @
2

2 2

+5VALW_BST_25 1 2 +5VALW_BST_R_25

PR5601
1/10W_10_5%_0603

8A
PU5601 1
PJ5601 RT6258CGQUF_UQFN12_3X3
2 1 +5VALW_VIN 5 1 PC5603 1.5UH_PCMB063T-1R5MS_10A_20%
V9B+ 2 1
PC5602
VIN BOOT 0.1U_25V_K_X5R_0402
PL5601 PJ5602
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

2
JUMP_43X79 1 1 8A
0.01U_0402_25V7K
1

@ 1 2 +5VALW_VCC_20 11 2 +5VALW_LX 1 2 +5VALW_P 1 2

6258C_AGND VCC LX1 1 2 +5VALW
PC5601

PC5604

PC5605

3
2 2 1U_0402_10V6K LX2 JUMP_43X118
2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1 1 1

1
@

PC5606

PC5607

PC5608

PC5609

PC5610

PC5611
1
+5VALW_EN1 6 10 +5VALW_P PR5602 PR5615
EN VOUT 1
1/8W_2.2_5%_0805 PR5603 1K_0402_1%
EMC_NS@ EMC_NS@ @ 1/16W_10K_1%_0402 2 2 2 2 2 2

PC5617
820P_50V_K_X7R_0402
@
2

2
7 9 +5VALW_FF +5VALW_SNB_20
PGOOD FF

2
+5VALW_FF_R
@ 1
1 2 0_0402_5% PC5613
[44] EC_ON
100mA 1000P_50V_K_X7R_0402 1

100P_0402_50V8J
PR5606 12 8 EMC_NS@

PC5616
+5VLP LDO5 AGND 6258C_AGND 2
1
0.1U_0402_10V7K
1

4
PC5618

PC5614 PGND 2
1

PR5605 4.7U_6.3V_K_X5R_0402
2
2

68K_0402_1% +3VALW PJ5604

Vset=5.1V±1% 3

1 2
Design Current:8A
2

PR5604
JUMPER
OCP: Min:9A, Max:11.8A
@
+5VALW_USM_R 100K_0402_5%
6258C_AGND
OVP=(1.15~1.25)*Vout
UVP=0.6*Vref
2
1

PQ5601
Fsw=750Khz
[44,55] +5VALW_PG
2 PJ5603
[44] EC_USM SSM3K15AMFV_2-1L1B
+5VLP
1
1 2
2
+5VL USM mode: 0.8V <EN1<1.7V
3

@ JUMP_43X39
PFM mode: 2.3V <EN1

4 4

Security Classification LCFC Highly Confidential Information Title

<Title>
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 54 of 60
A B C D
 5 4 3 2 1

@
PR9800 1 2 0_0402_5% P_LV5116A_EN
44,54 +5VALW_PG
@
PR9801 1 2 0_0402_5% VTT_EN
5 CPU_DRAMPG_CNTL
@
PR9802 1 2 0_0402_5% +1.8VALW_EN
44 EC_ON_1.8V V9B+
@
PR9803 1 2 0_0402_5% VDDQ_VPP_EN
44 EC_VPP_PWREN

2
D
+5VL D
PR9804
2.2_0603_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 P_LV5116A_VCC_30 P_LV5116A_VSYS_10

1
2

2
PC9800

PC9801

PC9802

PC9803
2
PR9806 1
+5VALW 2.2_0603_5% PC9805

1
1U_0402_10V6K PC9804
@ @ @ @ 1 0.1U_25V_K_X7R_0402 +3VALW
2 PJ9807 @
2 1 2 1
2 1 1A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2
PR9808
2.2_0603_5% PC9806 JUMP_43X39
1U_0402_10V6K
1 PU9800
1 1
6

PC9807

PC9808
36 VSYS @
VCC
P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2 +1.8VALW
PVCC V1P8A_IN
P_VDDQ_UG_30 1
PR9810 @ VDDQ_HG 25 P_+1.8VALW_LX_S 1 2 +1.8VALW_P 1 2 4A
V1P8A_PH1 1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 2P_VDDQ_BST_R_30 1 2 P_VDDQ_BST_30 40
VDDQ_BOOT

1
26 PL9800 PJ9803
PC9892 0_0603_5% V1P8A_PH2 2 1 PR9812 1UH_PCMB053T-1R0MS_7A_20% JUMP_43X79
P_VDDQ_LX_30 2 29 +1.8VALW_P +3VALW
0.1U_25V_K_X5R_0402
VDDQ_PH V1P8A_SNS
JUMP_43X39 4.7_0603_5% @
P_VDDQ_LX_SENS_10 39 9 P_VDDQ_VPP_IN
PC9816
10U 6.3V M X5R 0402 2
PJ9808 @
1 1A EMC_NS@ 1 1 1 1
VDDQ_SWSNS VPP_IN 2 1

1 2
P_VDDQ_LG_30 3 8 P_VDDQ_VPP +VDDQ_OUT

PC9809

PC9812

PC9810

PC9811
VDDQ_LG VPP 2 2 2 2
13 P_VTT_IN_30 1A 2
@
1
PC9814
1200P_50V_K_X7R_0402
P_VDDQ_SENS_10 VTT_IN 2 1

2
12
2 1 VDDQ_SNS 14 P_VDDQ_VTT PJ9809
EMC_NS@
VTT
PC9893 @ 2 1 JUMP_43X39 @ +0.6VS
0.1U_25V_K_X7R_0402 15
P_VCCIN_AUX_EN_10 23 VTT_SNS
AUX_DRVEN
PC9894
10U 6.3V M X5R 0402 P_VDDQ_VTT 1 2 1A
P_LV5116A_DDR_ID_10 1 2

10U 6.3V M X5R 0402

28
P_VCCIN_AUX_PWM_10 21 DDR_ID PJ9805
AUX_PWM P_LV5116A_AUX_CS_10 1
20 PR9816 1 21/16W_240K_1%_0402

PC9817
JUMP_43X39
AUX_CS
5 P_LV5116A_VDDQ_CS_10 PR9817 1 21/16W_240K_1%_0402 +3VALW +3VALW
@
@ P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
PR9818 1 2 0_0402_5% P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
13 VCCIN_AUX_VCCSENSE P_VCCIN_AUX_VCCSENSE_10 19 P_LV5116A_V1P8A_CTRL_10 +VCCIN_AUX OCP=41A

2
AUX_SNS V1P8A_CTRL
24 +2.5V_DDR
2
PC9818
30 P_LV5116A_AUX_SET_10 +VDDQ OCP=13A
C @
1000P_0402_50V7K
@ AUX_SET
PR9828
100K_0402_5%
PR9829
100K_0402_5% P_VDDQ_VPP 1 2 1A C
1 2

22UC_6.3VC_MC_X5RC_0603
P_VCCIN_AUX_VSSSENSE_10 2 0_0402_5% P_LV5116A_PROCHOT#
1

PR9819 1 2 0_0402_5%
6,13,44 H_PROCHOT# PR9820 1 7
13 VCCIN_AUX_VSSSENSE PROCHOT# VCCIN_AUX_VID0

1
16 PJ9802
PR9821 1 2 100K_0402_5% P_VCCIN_AUX_PG_1011 AUX_VID0 VCCIN_AUX_VID0 13,46 JUMP_43X39
+3VALW PG_ARAIL VCCIN_AUX_VID1
17
VDDQ_PGOOD AUX_VID1 @

10U 6.3V M X5R 0402

PR9823 1 2 100K_0402_5% 10 VCCIN_AUX_VID1 13,46
+3VALW PG_DDR P_LV5116A_CLK_5

2
33 PR9824 1 2 0_0402_5%

PC9813
44 VDDQ_PGOOD @ EC_SMB_CK3 44 1 1
SCL

PC9815
34 P_LV5116A_DAT_5 PR9825 1 @ 2 0_0402_5% PR9833 PR9834
P_LV5116A_EN 38 SDA EC_SMB_DA3 44
10K_0402_5% 10K_0402_5%
@ PMIC_EN @ @ 2 2
2 PR9827 P_LV5116A_DIGITAL_CTL_10

1
0_0402_5% 1 37 @
10K_0402_5% 1 2 PR9826 DIGITAL_CTRL 18 P_VCCIN_AUX_VSSSENSE_10
+5VL +1.8VALW_EN 35 AUX_RGND +5VALW +5VALW +5VALW
SLP_SUS#

100K_0402_5%
VDDQ_VPP_EN 32 41
DIGITAL_CTRL Control Mode SLP_S4# GND

0_0402_5%

10K_0402_5%
2

2
VTT_EN 31
AUX_VID1 AUX_VID0 Vout_AUX

PR9830

PR9831

PR9832
DDR_VTT_CTRL
High HW Control
0 0 0V
P_LV5116A_DDR_ID_10 @

1
Low SW Control LV5116AGQW_WQFN40_5X5 P_LV5116A_V1P8A_CTRL_10
@
P_LV5116A_AUX_SET_10 0 1 1.1V

0_0402_5%

10K_0402_5%

10K_0402_5%
2

2
P_VCCIN_AUX_VIN_S V9B+ 1 0 1.65V

PR9835

PR9836

PR9837
AUX_SET VCCIN_AUX Internal RAMP
PJ9806
1 2 3A High RAMP1
1 1 1.8V
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603 1 2

1
@ @
0.1U_0201_25V6-K

P_VCCIN_AUX_BST_R_30 JUMP_43X79
Low RAMP2 DDR_ID Type VPP VDDQ VTT/VDDQTX
P_VCCIN_AUX_BST_30

PC9820

PC9821

PC9822

@
EMC@

+5VALW 1 1
1

PR9839 @
1 2 1 2
Floating RAMP3 Low DDR4 2.5V 1.2V VDDQ/2(VTT)
2

2 2
--
PC9819 0_0603_5%
2

0.22U_25V_K_X5R_0402 Floating LPDDR4 1.8V 1.1V

PR9840
2.2_0603_5% PQ9800 DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence V9B+
2

PU9801
4 P_VCCIN_AUX_UG_30
1
High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX)
P_VCCIN_AUX_VCC_30 BOOT +VCCIN_AUX
1

8 High Low V1P8A follow PMIC_EN

VCC 3 P_VCCIN_AUX_UG_30
P_VCCIN_AUX_PWM_10 UGATE PJ9810
1.5A
1U_0402_10V6K

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
PWM 2 P_VCCIN_AUX_LX_S 7 P_VCCIN_AUX_LX_S 1 2 P_VDDQ_VIN_S 1 2
P_VCCIN_AUX_EN_10 PHASE High High V1P8A follow SLP_SUS# 1 2
1

330U_D2_2.5VY_R9M
1
PC9823

PL9801
EN 7 P_VCCIN_AUX_LG_30 6 0.22UH_CMMS063T-R22MS2R107_26A_20%

5
LGATE 1 JUMP_43X79
6

PC9828

PC9827
Low Low V1P8A follow PMIC_EN PQ9801 1 1 1

D
GND1
2

B 9
PC9825

PC9826
B
@

EMC_NS@
+ AONR32340C_DFN8-5
GND2
2

AON6982_DFN8-7 PR9842 PJ9800

RT9610CGQW_WDFN8_2X2 2.2_0805_5% JUMPER Low High V1P8A follow I2C P_VDDQ_UG_30
3
4
5

@ 2 4 2 2 2
EMC_NS@ G
1
2

S3
S2
S1
place close to VCCIN_ALX LMOS drain +VDDQ_OUT +1.2V
1

8A

3
2
1
PC9829
PL9802
1000P_0201_50V7-K PJ9804
P_VCCIN_AUX_LXSENS_10 P_VDDQ_LX_30
2

Rdson=2.8mohm@Vth=4.5V EMC_NS@ 1 2 1 2
1 2
PQ9803
0.47UH_PCMB053T-R47MS_13A_20% JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
AON7380_DFN8-5

5
@

2
PJ9801 1 1 1 1 1 1

PC9830

PC9831

PC9832

PC9833

PC9834

PC9835
+VCCIN_AUX VCCIN_AUX Vout CAP Config Vboot=1.8V Loadline=6mΩ 4.7_0603_5% JUMPER
P_VDDQ_LG_30
PR9844 @

1
4
AC+DC Ripple=(-10%~+5%)*VOUT EMC_NS@ 2 2 2 2 2 2
#1:Pure MLCC 22U/0603*20pcs

1
TDC=14A Iccmax=32A Rdson=10.5mohm@Vth=4.5V
place close to VDDQ LMOS drain

1
#2:POSCAP+MLCC 330U/9mohm*1pcs+22U/0603*7pcs CURRENT LIMIT=45A @ @

3
2
1
PC9851
Max Overshoot:2.13v/500us 1200P_50V_K_X7R_0402

2
EMC_NS@
OVP=(1.2~1.3)*Vref
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

P_VDDQ_LX_SENS_10 P_VDDQ_SENS_10

UVP=(0.45~0.55)*Vref
1

1
PC9836

PC9837

PC9838

PC9839

PC9840

PC9841

PC9842

PC9843

PC9844

PC9845

PC9846

PC9847

PC9848

PC9849

PC9850

PC9895

PC9896

PC9897

Fsw=600Khz
2

@ @ @ @ @ @ @ @ @ @ @ @ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1

1
PC9863

PC9858

PC9864

PC9866

PC9871

PC9853

PC9854

PC9855

PC9856
PC9859

PC9860

PC9861

PC9862
2

A A

@
@
@ @ @ @
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1 1 1 1 1 1 1 1 1
PC9872

PC9875

PC9877

PC9880

PC9881

PC9882

PC9883

PC9884

PC9885

PC9886

PC9887

2 2 2 2 2 2 2 2 2 2 2
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-LV5116

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
@ @ @ @ @ @ @ @ @ @ @
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
HS45A/HS55A 0.1

Date: Monday, November 02, 2020 Sheet 55 of 60

5 4 3 2 1
 5 4 3 2 1

VCCIN
Vboot=1.8V Loadline= 2mohm PDG: 4*220UF(7343)+ 10*22UF(0603)+12*10UF(0402)
Ripple=30mV(0A~1A) S350: 2*330UF(B2)+ 10*22UF(0603)+12*10UF(0402)+3*1UF(0201)
Ripple=30mV(1A~5A)
PU3500 +VCCIN
Ripple=15mV(5A~TDC)
+5VALW P_VCCIN_VIN_S TDC=40A Iccmax=65A

330U_B2_2.5VM_R9M

22UC_6.3VC_MC_X5RC_0603
PR3503 PR3504
OCP=85A

330U_B2_2.5VM_R9M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1/10W 6.2 1% 0603 2.2_0402_1% U42@
1 2 P_RT3613EE_VCC_20 24 8 P_RT3613EE_VIN_101 2
VCC VIN Max Overshoot:200mv/500us 1 1 1

PC3570
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC3502

PC3503
OVP=VID+400mV

PC3571

PC3572

PC3573

PC3574

PC3575

PC3576

PC3577

PC3578

PC3579

PC3580

PC3581

PC3584

PC3585

PC3586

PC3587

PC3588

PC3589

PC3590

PC3591

PC3592

PC3593
2 + +

1
@2
PC3506
4.7U_0402_6.3V6M
PC3507
0.1U_0402_25V7-K
UVP=VID-150mV 2 2 @2 2 @2 2 2
@
2
@
2 2 2 2 2 2 2 2
@
2
@
2 2
@
2 2
@
2 2
1

2
D Fsw=1000 Khz @
D

16 12 P_VCCIN_PWM1_10
[44,53] VR_HOT# VR_HOT# PWM1

RT3613EE_VREF

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

26 13 P_VCCIN_PWM2_10
VREF06 PWM2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC3531

PC3582

PC3535

PC3583

PC3533

PC3536

PC3537

PC3538

PC3534

PC3539

PC3526

PC3527

PC3540

PC3532

PC3541

PC3542

PC3528

PC3529

PC3530
1 @ @
PR3508 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3.9_0402_1% 11
P_VCCIN_VREF06_R_10 PWM3
19.6K_0402_1%
10K_0402_1%

12.1K_0402_1%

2M_0402_1%
1

2 2

P_VCCIN_Driver_EN_10 15
PR3509

PR3510

PR3511

PR3512

DRVEN @ @ @ @ @ @ @ @ @ @
PC3510

1
@ 0.47U_0402_25V6K
1

@ PR3513 3.9K_0402_1%
2

100K_0201_5% PR3514
PR3515 4 P_VCCIN_ISEN1P_R_10 1 2 P_VCCIN_ISEN1P_10
ISEN1P

1
110K_0402_1% @

2
1 2 PR3516
@ 1.4K_0402_1% PC3511
PR3517 0.1u_0201_10V6K
P_VCCIN_TSEN_R_10 P_VCCIN_TSEN_10 P_VCCIN_ISEN1N_R_10 1 P_VCCIN_ISEN1N_10

1
1 2 7 3 2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
TSEN ISEN1N

2 2
1 1 1 1 1 1 1 1 1

PC3544

PC3548

PC3550

PC3551

PC3553

PC3555

PC3560

PC3562

PC3565
PH3501 1/16W_680_1%_0402 U42@
100K_0402_1%_TSM0B104F4251RZ PC3517 PR3519
P_VCCIN_SET1_10 22
P_VCCIN_SET2_10 SET1 P_VCCIN_ISEN2P_R_10
0.1u_0201_10V6K 3.65K_0402_1% @2 @2 @2 @2 @ @ @2 @2 @2
2 P_VCCIN_ISEN2P_10

1 1
21 1 1 2 2
P_VCCIN_SET3_10 SET2 ISEN2P

2
20 PR3564
SET3
1/16W_15.4K_1%_0402

2
U22@ 0_0201_5% PR3520
10K_0402_1%

14K_0402_1%

1.33K_0402_1% PC3518
8.25K_0402_1%
1

1
PR3524

PR3526 @ PR3527 U42@ 0.1u_0201_10V6K

P_VCCIN_EN_10 9 P_VCCIN_ISEN2N_R_10 P_VCCIN_ISEN2N_10

1
1 2 2 1 2
PR3522

PR3523

PR3525

[44] EC_VR_ON VRON ISEN2N U42@

2 2
@ 0_0402_5% 1 1/16W_680_1%_0402
U42@

10K_0201_1%
1
P_VCCIN_SET2_R_10 P_VCCIN_TSEN_REF_10
PC3519 PC3520
+5VALW PDG: VCCIN
2

14

PR3563
100P 25V J NPO 0201 0.1u_0201_10V6K
@ 2 NC1 P_VCCIN_ISEN3NP_10 U22@

1
@ 5
P_VCCIN_SETQ_R_10 P_VCCIN_SET3_R_10 ISEN3P U42@

1
Value Qty Note
1/16W_348_1%_0402

1/16W_237_1%_0402

PR3536
330_0402_1%

P_RT3613EE_VCC_20
49.9_0402_1%
1

2
1 2 100K_0402_5%
32 12
PR3531

PR3532

PR3533

PR3534

NC2 10u_0402 Secondary Side

Put them as directly below the BGAs as possible.
@ 6 PR3535
ISEN3N

2
10K_0402_5%
220u_7343 2
2

C Primary Side C
P_RT3613EE_ANS_10 MLCC cap recommendation based on VR solution
with 150kHz VR bandwidth or 600kHz switching
220u_7343 2 frequency, assuming BW=1/4 of Fsw. Place board
caps as close as possible to package in this order

1
(Place holder) where 0402 to be closest to package pins:

1
PR3538 VR->7343->0603->0402->Package
@ 100K_0201_5% PQ3505
P_SVID_VCLK_5
22u_0603 8
19 31 2
VCLK ANS_EN

2
EC_ANS [44]
SSM3K15AMFV_2-1L1B

3
ANS@
P_SVID_DAT_5 18 28
+VCCST_CPU VDIO VSEN PC3524
PC3523
330P_0402_50V8J
1 2
150P_50V_J_NPO_0402 1 2
2

P_SVID_ALERT#_5 17 29 P_VCCIN_COMP_10
@ PR3539 ALERT# COMP PR3540 PR3541
54.9_0402_1% 1 @ 2 1 2 VCCIN_SENSE [12]
1/16W_28K_1%_0402 1/16W_8.45K_1%_0402
1

10 30 P_VCCIN_FB_10
[44] CPU_VR_READY VR_READY FB V9B+

1
1 @ 2 P_VCCIN_PSYS_10 PC3525
[44,53] PSYS
1000P_0402_50V7K PJ3501
+5VALW P_VCCIN_VIN_S

2
PR3542 @ 1 2

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
PC3516 1 2

22U_B2_25VM_R100M
1
0_0402_5% 2 23 27 VSSIN_SENSE [12] 1
0_0402_5% PSYS RGND 1 2 1 2 1 1 JUMP_43X118

0.1U_0201_25V6-K
P_VCCIN_IMON_NTC_10

1
PC3505

PC3568

PC3504

PC3500
PR3543 PR3501 +
2.2_0603_5% PQ3501 @
PR3544 PH3502 0.22U_16V_K_X7R_0402

U42@

U42@
AON6380_DFN8-5
1P_VCCIN_IMON_R_10 P_VCCIN_IMON_10

2
1 2 2 25 33 PR3502 2 2 2
@ IMON GND
100K_0402_1%_TSM0B104F4251RZ
PR3546
2.2_0603_5%
PU3501 4 +VCCIN
54.9_0402_1% 4 P_VCCIN_BST1_30
RT3613EE_VREF P_VCCIN_VCC1_30 8 BOOT

1
2 PR3545 1 2 @ 1
RT3613EEGQW_WQFN32_4X4 VCC P_VCCIN_UG1_30
@ PR3505 @ 3
P_VCCIN_PWM1_10 P_VCCIN_PWM1 UGATE PL3501

1U_0402_10V6K
1 2 5
21K_0402_1% 11.3K_0402_1% PWM P_VCCIN_PH1_S

3
2
1
0_0402_5% @ 2 1 2
P_VCCIN_Driver_EN_10 P_VCCIN_EN1_10 1 PHASE

1
1 2

PC3508
0.22UH_CMMS063T-R22MS2R107_26A_20%
EN P_VCCIN_LG1_30

1
0_0402_5% 7
6 LGATE
PR3506
GND1
PQ3502 PR3507 @ @

2
9 AON6324_DFN8-5 2.2_0805_5%
GND2 EMC_NS@ PJ3502 PJ3503

1
RT9610CGQW_WDFN8_2X2 P_VCCIN_PH1_SN_S JUMPER JUMPER

P_VCCIN_ISEN1P_10 1

P_VCCIN_ISEN1N_10 1
4 PC3599
2200P_0402_50V_X7R_0402

1
B Virtual Symbol PC3509
1000P_0201_50V7-K B

3
2
1

2
EMC_NS@
+VCCST_CPU
U22 U42
1/16W_45.3_1%_0402

PR3509 200K SD03420038J 93.1K SD03493128J

100_0402_1%
75_0402_1%
1

PR3522 19.6K SD00000358J 22.6K SD000019W00

PR3549

PR3548
PR3547

@ PC3543
PR3531 232 SD00001THS0 0 SD02800008J 1U_0402_6.3V6K
2
2

PR3512 178K SD03417838J 19.6K SD00000358J PR3550

P_SVID_VCLK_5 1
@
2
PR3525 8.45K SD000011R00 14K SD03414028J 0_0402_5%
VR_SVID_CLK [12] V9B+
PR3544 11.8K SD03411820J 15.4K SD03415428J PR3551
P_SVID_ALERT#_51
@
P_VCCIN_VIN_S
PJ3504
2 1 2

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
VR_SVID_ALERT# [12]

22U_B2_25VM_R100M
1 2
PR3545 24.3K 20.5K SD03420528J 0_0402_5% 1
SD000011300

0.1U_0201_25V6-K
+5VALW 1 1 JUMP_43X118

1
PC3513

PC3514

PC3515

PC3501
PR3546 16.2K SD00001AZ00 10.5K SD03410528J P_SVID_DAT_5
PR3552 @
PC3512
+
@
1 2
VR_SVID_DATA [12] 1 2 1 2
PR3514 2.37K SD03423718T 3.65K SD03436518J 0_0402_5%

2
PR3518 2 2 2
PR3516 1.82K SD00001860T 1.33K SD00000RF0J 2.2_0603_5%
0.22U_16V_K_X7R_0402
PQ3503

2
U42@ AON6380_DFN8-5
PR3521 U42@ U42@
PR3540 42.2K SD03442228J 18.2K SD03418228J
U42@
2.2_0603_5%
U42@ PU3502 4 U42@ +VCCIN
4 P_VCCIN_BST2_30
P_VCCIN_VCC2_30 8 BOOT

1
PR3528 VCC 3 P_VCCIN_UG2_30 U42@
P_VCCIN_PWM2_10 P_VCCIN_PWM2 UGATE PL3502
1U_0402_10V6K
1 2 0_0402_5% @ 5
PWM P_VCCIN_PH2_S

3
2
1
PR3529 2 1 2
P_VCCIN_Driver_EN_10 2 P_VCCIN_EN2_10 1 PHASE
1

1
PC3521

0.22UH_CMMS063T-R22MS2R107_26A_20%
EN P_VCCIN_LG2_30

1
0_0402_5% @ 7
6 LGATE
U42@
GND1
PQ3504 PR3530 @ @
2

2
9 AON6324_DFN8-5 2.2_0805_5%
GND2 U42@ EMC_NS@ PJ3505 PJ3506

1
RT9610CGQW_WDFN8_2X2 P_VCCIN_PH2_SN_S JUMPER JUMPER

P_VCCIN_ISEN2P_10 1

P_VCCIN_ISEN2N_10 1
4 PC3598
U42@ 2200P_0402_50V_X7R_0402

1
U42@
PC3522
1000P_0201_50V7-K

3
2
1

2
EMC_NS@

A A

Security Classification LCFC Highly Confidential Information Title

<Title>
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
HS45A/HS55A 0.1

Date: Monday, November 02, 2020 Sheet 56 of 60

5 4 3 2 1
 A B C D

V9B+
PJ9902 @
1.5A 2 1 PC9902
2 1 PR9900 0.1U_0603_25V7-M

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
+1.35V_BST 1 2+1.35V_BST_R 1 2
JUMP_43X79 1 1

PC9900

PC9901
OPT@ 10_0603_5%
OPT@
OPT@ +1.35VGS
PD9900 2 2 PU9900

18

5
1 2 PL9900
PJ9901
0.68UH_PCMB063T-R68MS_16A_20%
8A

AGND

VBOOT
LRB751V-40T1G_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1
VIN4 SW _1 2 1
OPT_NS@ OPT@ OPT@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
+1.35V_EN
OPT@ JUMP_43X118
1 23 FBVDDQ_PWR_EN 1 2 16 4 1 1 1 1 1 1 1

PR9901 EN4 SW _2 @

PC9905

PC9906

PC9907

PC9908

PC9909

PC9910
1
100K_0402_5% 1 2 PC9903 OPT@ PC9904 OPTNS@
0.022U_0402_25V7K 15 +1.35V_FB 1 2 PR9902
OPT@ FB 2 2 2 2 2 2
25 2.2_0603_5%
NC_3

1
0.1U_0402_25V6 EMC_OPTNS@

OPTNS@

OPTNS@
23

OPT@

OPT@

OPT@

OPT@
PR9903
NC_2

2
22 1K_0402_1%

+1.35V_SN
NC_1
OPT@

1
6
PGND_1

2
+5VALW

1
7 PR9904
2 1 PC9911 24 PGND_2 PC9912 +1.35V_FB_1 42.2K_0402_1%
1U_0402_6.3V6K VCC_SW 8 1000P_0402_50V7K
PGND_3 OPT@

2
1
EMC_OPTNS@ PC9913
OPT@ 9
1.8VGS_PWR_EN 1
PR9905 0_0402_5%
2 MAIN_PWR_EN 19 PGND_4
560P_0402_50V7-K
OPT@
Vout=1.35V±5%
23,26 1.8VGS_PWR_EN EN2

2
+3.3V_1.8V_AON 10
@
PGND_5 Vset=1.36V±2%
+1.35V_FB

2
1 2 PC9915 21 11
PC9914
VIN2 PGND_6 OCP>12A
0.1U_0402_25V6 1U_0402_6.3V6K
0.5A PJ9907

1
OPT_NS@ OPT_NS@ +3V_1.8VGS
Vref=0.6V

1
20 +3V_1.8VGS_R 2 1
VOUT2 @ 2 1 0.5A
PXS_PWR_EN_R 28 1 2
PR9907
31.6K_0402_1%
OVP=(1.25~1.35)*Vref
23 PXS_PWR_EN_R EN3 JUMP_43X39
PC9917
PJ9906
OPT@
UVP=(0.7~0.8)*Vref

2
PC9916 +3.3V_1.8V_AON_IN 1U_0402_6.3V6K OPT@ +3.3V_1.8V_AON
2 1 26 +3.3V_1.8V_AON_R 2 1
0.1U_0402_25V6
VIN3_1 VOUT3_1 @ 2 1 Fsw=700Khz
OPT_NS@
2 27
1A
1A VIN3_2 VOUT3_2 JUMP_43X39 LSW1 RDS=36~50mohm,Io=0.5A
1

1
29
PC9919 VIN3_3
PC9918
1U_0402_6.3V6K
LSW2 RDS=18~25mohm,Io=1A
1U_0402_6.3V6K OPT@ LSW3 RDS=5~7mohm,Io=3.5A

TH_ALT

PGOOD
1

2
VCC
OPT_NS@

14

17

13
+1.35V_VCC
2

1
2 2

PR9908 PR9909
100K_0402_1% 100K_0402_1%
OPT_NS@ OPT_NS@

2
1
PC9920
1U_0402_6.3V6K

2
OPT@

+3.3V_1.8V_AON_IN
+3VS
PR9910
2 1
0_0402_5%
+1.8VALW
OPTN16@
PR9911
2 1
0_0402_5%
OPTN17@

3
+3VALW 3

+3VALW

2
PC9921 PR9912 +1.0VGS
1U_0402_6.3V6K
+1.8VALW 100K_0402_5%

2
OPT@ PJ9905
1A

1
+1.0V_P 2 1
1A PJ9908 6
PU9901
7 @ 2 1
VCNTL POK

1/20W_100K_1%_0201 1/20W_24.9K_1%_0201
2 1 +1.0VGS_VIN 5
2 1 VIN JUMP_43X39 Vout=1.0V±5%

2
3

220P_0402_50V7K
4.7U_0402_6.3V6M

VOUT1

1
4 @

PR9913

PC9924
1 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X39 PC9922 8 VOUT2
EN

1
@ PC9923 9 2 OPT@

GND
EPAD FB

2
4.7U_0402_6.3V6M

PC9925

PC9926
1
2 2 @
@ OPT@

2
+1.0V_FB

1
APL5930CKAI-TRG_SO8 @ OPT@

1
OPT@

PR9915
PR9916 1 2 0_0402_5% @ 1.0VGS_EN OPT@
23 PXE_VDD_EN_R

2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR-VGA-PMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document
Size DocumentNumber
Number Rev
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date:
Date: Monday, November 02, 2020 Sheet
Sheet 57 of 60
A B C D
 5 4 3 2 1

PWM-VID Specification
N17 Config N16 Config B RT8816 PSI UP1666 PSI Phase Configuration
Vmin(V) 0.3 0.6 1.6V~5.5V 1.6~5.5V 2Phase CCM
Vmax(V) 1.3 1.2 1.08~1.35V 1~1.4V 2Phase DEM
Vboot(V) 0.8 0.9 0.7~0.88V 0.4V~0.8V 1Phase CCM
Vstep(mV) 6.25 6.25 0~0.4V 0~0.2V 1Phase DEM
N(level) 160 96
Fpwm(KHz) 675 1.125 V9B+
Tdmin(nS) 9.26 9.26 +VGA_CORE_VIN PJ7000
D D
1 2
T(uS) <100 <100 1 2 4A
JUMP_43X79
+5VALW

1U_25V_K_X5R_0402
@

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_0201_25V6-K
1 1 1

EMC_OPTNS@

1
PC7000

PC7001

PC7002

PC7003
PQ7000

2
2 2 2

1
OPT@

5
PR7000 AON6380_DFN8-5
PU7000
2_0603_5%
OPT@ @
OPT@ OPT@

2
NVVDD_PVCC 18
PVCC 2 NVVDD_HG1 4
UGATE1

1
+3.3V_1.8V_AON PC7004 PR7003
PC7005
1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K
1 NVVDD_BS1 1 2 1 2
OPT@ BOOT1 OPT@

3
2
1
1

21
PR7001 GND OPT@
5.1K_0402_1%
PL7000 +VGA_CORE
20 NVVDD_PH1 NVVDD_PH1 1 2
OPT@ PHASE1
OPT@

2200P_0402_50V7K 1/8W_1_5%_0805
EMC_OPTNS@
PR7002
2

1
PQ7001 0.22UH_PCMB063T-R22MS_23A_20%
1 2 0_0402_5% NVVDD_PSI_R 4 AON6324_DFN8-5

PR7004
26 PSI_VGA OPT@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PSI

330U_D2_2V_Y
1
PR7005 OPT@ PR7006OPTNS@ 1 1 1 1 1 1
1 2 1 2 +

PC7007

PC7009

PC7010

PC7011

PC7012

PC7013

PC7014
+3VS

2
1K_0402_1% 5.1K_0402_1% 19 NVVDD_LG1 4
13 LGATE1
PGOOD 1 2 2 2 2 2 2 2
8,23 DGPU_PWROK
PR7007
OPT@
OPT@

PC7008

EMC_OPTNS@
1 2 NVVDD_EN_R 3
23 NVVDD_EN EN

3
2
1
PD7000 OPT@ 2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@
1

1/16W_23.2K_1%_0402 PC7015
C
1 2 0.1U_0402_10V7K +VGA_CORE_VIN V9B+ C

OPT@ PJ7001
2

1 2
1 2
RB521CM-30T2R_VMN2M-2 PQ7003 1 2 4A

1U_25V_K_X5R_0402
NVVDD_VID_R NVVDD_HG2

5
PR70081 2 5 14 AON6380_DFN8-5

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

0.1U_0201_25V6-K
26 NVVDD_PWM_VID VID UGATE2 JUMP_43X79
OPT@ 1 1 1
1

1
0_0402_5% OPTNS@ PR7009 @

PC7018

PC7019

PC7020

PC7021
PC7017
PC7016 2.2_0603_5%
OPT@ 0.1U_0402_10V7K 15 NVVDD_BS2 1 2 1 2
BOOT2
2

2
4 2 2 2
OPT@ 0.22U_0603_25V7K +VGA_CORE
OPT@ PL7001 @
09/08 change 1U to 0.1uh OPT@ OPT@

EMC_OPTNS@
3
2
1
16 NVVDD_PH2 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2

2200P_0402_50V7K 1/8W_1_5%_0805

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
EMC_OPTNS@
VREF PQ7004

1
0.22UH_PCMB063T-R22MS_23A_20% 1

330U_D2_2V_Y
5
PC7022 AON6324_DFN8-5

PR7010
OPT@ 1 1
1

0.1U_0402_25V7-K +

PC7023

PC7024

PC7025
OPT@
PR7011 OPT@
20.5K_0402_1%

2
2 2 2
OPTNS@ 17 NVVDD_LG2 4
LGATE2 1
2

OPT@

OPT@

OPT@
PC7026

EMC_OPTNS@
NVVDD_REFIN

1
7
REFIN PR7012 2

3
2
1
2

30K_0402_1% PR7015
1

PR7014 UPI_OPT@ 100_0402_1%

PR7013 82.5K_0402_1% 1 2

2
16.5K_0402_1% UPI_OPT@
OPTNS@ PR7017 OPT@
PR7016
1

6.19K_0402_1%
PR7018 Vboot=0.8V
2

1 2 1 2 NVVDD_VIDBUF 6
REFADJ NVVDD_FBRTN
1

10 1 2
PC7027
0.01U_0402_25V7K 4.32K_0402_1%
OPTNS@ RGND NVVDD_VSS_SENSE 22 Ripple=±20mV
B B
1

OPTNS@ OPTNS@ 0_0402_5% OPT@ TDC=28.5A Iccmax=55A OCP>75A

2

PR7019 PC7028
11 NVVDD_FB
309_0402_1% 4700P_0402_25V7-K
VSNS VR Remote Sense - Tie to GPU sense points TDC=30A Iccmax=60.1A OCP>80A
OPTNS@ OPTNS@
2

1
PR7020
PC7029
Vref=2V
2

1000P_0402_25V7-K
2 1NVVDD_FS 9 12 NVVDD_SS
TON OCSET/SS OPTNS@ PR7021 OPT@ FUVP:Vfb=0.2V

2
V9B+ 475K_0402_1% 1 2
SUVP:Vcomp=3V
COMP---UPI NVVDD_VCC_SENSE 22
PR7022 RT_OPT@
2 1 PR7023
0_0402_5%
OVP:Vfb=2V
2.2_0603_5%
100_0402_1%
1 2 +VGA_CORE
Fsw=320KHz
UP1666QQKF_WQFN20_3X3
RT_OPT@
1

UPI_OPTNS@
1000P_0402_25V7-K
1

PC7030 OPTNS@
PR7025 RT_OPT@ OPT@
1000P_0402_25V7-K
1

1U_0402_25V6-K
2

51K_0402_1%
PC7031

110K_0402_1%

RT_OPT@ PR7024
2

UPI_OPT@
PC7032

PR7026
2

100K_0402_1%
UPI_OPT@
2

PR7027
1
2

0_0402_5%
2
2

1 2 NVVDD_FBRTN PC7033
1000P_0402_25V7-K
UPI_OPT@ UPI_OPT@
PR820,PR819,PC849 set TON for RT8816 RT_OPTNS@
1
2

PR7028
0_0402_5%
RT_OPT@ PR833,PR834 set FS/OC for UP1666
PR833=82.5,PR834=100k, OCP=85A
1

PR821 set OC and PC837 set external SS for RT8816

PR832,PC834,PR836 set COMP for UP1666
A
PR816,PR812,PR815,PR813,PR818,PC826 BOM structure control for N16 or N17 A

Component Value N17 N16

R1(KΩ) PR7017 6.19 20
R2(KΩ) PR7011 20.5 20
R3(KΩ) PR7016 4.32 2 UPI_OPT@ : for UP1666 Security Classification LC Future Center Secret Data Title
R4(KΩ) PR7013 16.5 18
R5(KΩ) PR7019 0.309 0 RT_OPT@ : for RT8816A Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
C(nF) PC7028 4.7 2.7 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Document Number
HS45A/HS55A Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, November 02, 2020 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 POWER CHANGE LIST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HS45A/HS55A
Date: Monday, November 02, 2020 Sheet 60 of 60
5 4 3 2 1