VHDL: A Complete Academic Guide
Preview Draft Edition
Author: Academic Project Draft
Table of Contents
Chapter Title
1 Introduction to VHDL & Digital Design
2 Basic Gates in VHDL
3 Combinational Circuits
4 Arithmetic Circuits
5 Sequential Circuits (Draft)
6 Structural vs Behavioral Modeling
7 Advanced Topics (Draft)
8 Practical Case Studies (Draft)
Chapter 1: Introduction to VHDL & Digital Design
VHDL (VHSIC Hardware Description Language) is a powerful language used to describe digital
systems. It allows designers to model, simulate, and implement circuits in hardware such as FPGAs
and ASICs.
Chapter 2: Basic Gates in VHDL
Example: AND Gate
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_Gate is Port ( A : in
STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end AND_Gate; architecture
Behavioral of AND_Gate is begin Y <= A AND B; end Behavioral;
Chapter 3: Combinational Circuits
Example: 4-to-2 Encoder (Structural with Port Map)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Encoder4to2 is Port ( I : in
STD_LOGIC_VECTOR(3 downto 0); Y : out STD_LOGIC_VECTOR(1 downto 0)); end
Encoder4to2; architecture Structural of Encoder4to2 is begin process(I) begin
case I is when "0001" => Y <= "00"; when "0010" => Y <= "01"; when "0100" => Y <=
"10"; when "1000" => Y <= "11"; when others => Y <= "00"; end case; end process;
end Structural;
Chapter 4: Arithmetic Circuits
Example: Ripple Carry Adder
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RippleAdder is Port ( A, B : in
STD_LOGIC_VECTOR(3 downto 0); CIN : in STD_LOGIC; SUM : out STD_LOGIC_VECTOR(3
downto 0); COUT : out STD_LOGIC); end RippleAdder; architecture Structural of
RippleAdder is signal C : STD_LOGIC_VECTOR(4 downto 0); begin C(0) <= CIN; gen:
for i in 0 to 3 generate SUM(i) <= A(i) XOR B(i) XOR C(i); C(i+1) <= (A(i) AND
B(i)) OR (A(i) AND C(i)) OR (B(i) AND C(i)); end generate; COUT <= C(4); end
Structural;
Chapter 5: Sequential Circuits (Draft)
This chapter will include Flip-Flops, Registers, Counters, and FSM design.
Chapter 7: Advanced Topics (Draft)
This chapter will include synthesis notes, timing analysis, and optimization techniques.
